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PCM1865EVM: configuration

Malay Dhrangadhria1
Prodigy 230 points
Part Number: PCM1865EVM
Other Parts Discussed in Thread: PCM1865

Hello, I am working with PCM1865evm to configure it with 4ch TDM interface. 

I am using external host iMX8M board as master and PCM1865 as slave. 

I need some help for PCM1865 slave configuration setting with PurePath tool for 4ch TDM interface. I have removed required registers to interface PCM1865 through external host and i am able to record 2 channel audio successfully with I2S interface. 

1. I am using PCM1865 as slave and iMX8M host board as master, In this case for 4ch TDM interface do i have to provide SCKI from iMX8M board (MCLK).

2. Below are the settings i have done for 4ch TDM interface with 16bit, Please let me know this is correct or not.?

{ADC_REG0_PGA_Val_1L, 0x08}, // PGA Value Channel 1 Left
{ADC_REG0_PGA_Val_1R, 0x08}, // PGA Value Channel 1 Right
{ADC_REG0_PGA_Val_2L, 0x08}, // PGA Value Channel 2 Left
{ADC_REG0_PGA_Val_2R, 0x08}, // PGA Value Channel 2 Right
{0x05, 0x86},  // default 
{ADC_REG0_ChanSel_1L, 0x41}, // ADC Input Channel Select ADC1L - VINL1[SE]
{ADC_REG0_ChanSel_1R, 0x41}, // ADC Input Channel Select ADC1R - VINR1[SE]
{ADC_REG0_ChanSel_2L, 0x42}, // ADC Input Channel Select ADC2L - VINL2[SE]
{ADC_REG0_ChanSel_2R, 0x42}, // ADC Input Channel Select ADC2R - VINR2[SE]
{0x0B, 0xDF}, // Receive PCM Word length - 16bit; TDM_LRCK_MODE - duty cycle of LRCK is 1/256}
{0x0C, 0x01}, // Select TDM transmission data. 01: 4ch TDM - DOUT1: ch1[L], ch1[R], ch2[L], ch2[R]
{0x20, 0x0F}, // SCK/Xtal selection; Slave mode, Enable Auto Clock Detector Configuration
  • 0
    TI__Mastermind 23050 points

    Hi Malay,

    It is not necessary to provide an SCKI to PCM1865 in slave mode as long as you are using a valid BCLK and FSYNC. Note BCLK/FSYNC of 128 is not supported. You also need to set your TX word length to 16-bit. RX word length is only used if you are also giving the device an I2S data input from another device.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 230 points

    Hello Zak, 

    Thank you for the clarification. 

    I believe for TDM BCLK/FSYNC should be 256. 

    I want more clarification on ADC channels configuration of PCM1865. Below is my understanding, Please correct if i am wrong. I am connecting 4 analog channel2 (2 stereo) to Vin1 (L1 and R1)and Vin2 (L2 and R2) inputs on PCM1865 board as shown in below figure for the reference.  

    For this configuration to get the 4ch TDM out from I2S port below is my register configuration as i have mentioned in earlier message, 

    {ADC_REG0_ChanSel_1L, 0x41}, // ADC Input Channel Select ADC1L - VINL1[SE]
    {ADC_REG0_ChanSel_1R, 0x41}, // ADC Input Channel Select ADC1R - VINR1[SE]
    {ADC_REG0_ChanSel_2L, 0x42}, // ADC Input Channel Select ADC2L - VINL2[SE]
    {ADC_REG0_ChanSel_2R, 0x42}, // ADC Input Channel Select ADC2R - VINR2[SE]
    {0x0B, 0xDF}, // Receive PCM Word length - 16bit; TDM_LRCK_MODE - duty cycle of LRCK is 1/256}
    {0x0C, 0x01}, // Select TDM transmission data. 01: 4ch TDM - DOUT1: ch1[L], ch1[R], ch2[L], ch2[R]
    I understand by this configuration i am able to get the TDM audio out as per the above reference frame from DOUT pin (orange test point).

  • 0 in reply to Malay Dhrangadhria1
    TI__Mastermind 23050 points

    Hi Malay,

    Your images did not come through, but your register configuration looks appropriate to me.

    Best,

    Zak