Hi Sir,
Could you advise how to config the registers about the following setting?
MCLK is 24.576Mhz, BCLK is 3.072Mhz and Fs is 48K.
Thanks, Ian.
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Hi Sir,
Could you advise how to config the registers about the following setting?
MCLK is 24.576Mhz, BCLK is 3.072Mhz and Fs is 48K.
Thanks, Ian.
Hi Sir,
Pls kindly help for check it, thanks.
Thanks, Ian.
Hello Ian,
Are you just looking for a Clock configuration for 48kHz with these input clocks? If so, 24.576MHz is an integer multiple of 48kHz so the PLL is not needed. By default, MCLK is selected as CODEC_CLKIN so this is fine. All that needs to be configured is MADC, NADC and AOSR. For 48kHz, NADC = 4, MADC = 1 and AOSR = 128.
Regards,
Aaron