TPA2037D1: Impacts of tying EN pin to a voltage greater than VDD+0.3v

Berry

Part Number: TPA2037D1

In our design, we have both 3.3V (for MCU/digital) and 2.8V (for audio/analog). The TPA2037D1 is on the 2.8V LDO but we accidentally tied its "EN" pin to a 3.3V GPIO signal with no voltage divider. That GPIO is driven by another TI part, CC3220. From the TPA2037D1 datasheet, the "ABSOLUTE MAXIMUM RATINGS" for the "EN" is VDD+0.3V, so in our case, the maximum allowed would be 3.1V (2.8+0.3). However, it's currently 3.3V so we're exceeding that by 200mV. Our prototype boards are already made and obviously we will fix this for production, but my questions are:

1. Is this catastrophic and will it cause a device failure ? What are the impacts of this oversight (keeping in mind that these boards are prototypes)?

2. The 3.3V GPIO is controllable and we can limit the current to the minimum setting allowed by the CC3220, would that be of any help?

3. What is the maximum "RECOMMENDED OPERATING CONDITION" for the EN pin? There isn't any "max" specified in the datasheet, only a min. Would the max recommended value be the same value as the absolute maximum in this case? (ie. VDD+0.3V)

Thanks!
Berry

over 3 years ago

0 Luis Fernando Rodriguez S. over 3 years ago

TI__Guru* 84915 points

Hi, Berry,

The absolute maximum rating should be always avoided since it may result in a permanent device damage if the pin is constantly exposed to this level. We cannot guarantee that the current limit will protect the device since the absolute maximum voltage is reached. There could be cases where the device is exposed to this value and it doesn't result in a damage immediately. However, after constant expose, in may present failures in long term.

The EN pin should be limited to the VDD level as maximum operating voltage.

Please let me know if you have additional questions or comments.

Best regards,
Luis Fernando Rodríguez S.

0 Berry over 3 years ago in reply to Luis Fernando Rodriguez S.

Prodigy 220 points

Understood, thanks Luis, I suspected that may be the case.

Regards,
Berry

0 Berry over 3 years ago in reply to Berry

Prodigy 220 points

Hi Luis

Is there any concern to tie the "EN" pin directly to VDD?

On our final board, it will be driven by an MCU GPIO (after divider), but for the prototype, we're planning to rework the PCB to connect the "EN" pin directly to VDD.

Thanks,
Berry

0 Luis Fernando Rodriguez S. over 3 years ago in reply to Berry

TI__Guru* 84915 points

Hi, Berry,

There's no problem if EN pin is directly connected to VDD. Actually, this is a practice that we do with some of our amplifiers EVMs.

Best regards,
Luis Fernando Rodríguez S.

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TPA2037D1: Impacts of tying EN pin to a voltage greater than VDD+0.3v