Hello,
i'm having issues simulating a single supply opa1641 as a buffer.
On the input, i have a sinewave, 100mv Vpp and a 100ohm internal resistance but the output is centered around 199mV. The singla amplitude is not the same at all. Do you have any idea why i'm getting this?
hank you
Hi Alassane,
I think that the DC biasing may be the issue. I duplicate what you had, if I understood what you are trying to do.
Generator or power source are low impedance source. From the above schematic, generator VG1||R2(100kOhm), so you do not have voltage divider anymore due to VG1. Your input at V+ is +/-100mV in AC (think the V1 12V as AC ground). Your output is not responding linearly with input, which it may be too close to Input common-mode voltage range.
/cfs-file/__key/communityserver-discussions-components-files/6/OPA1641-E2E-09102020.TSC
BTW, when you add voltage sources, you have to connect them in series. When you add current sources (high impedance device), you add them in parallel.
If you have additional questions, please let us know.
Best,
Raymond
hi,
this is almost what i want to except that i want to use the voltage divider biasing so V1 would not be on the schematic.
Vin would be a high impedance guitar pickup to which i want to add a DC offset as here:
I set Vin to 10k, it's better but Cin doesn't supress the DC component
Hi Alassane,
I was not sure what you wanted initially. Without adding additional components, Vin is AC coupled with the DC bias, since this is for audio application. I hope that this will meet your requirements. You may need to optimize the coupling capacitor C3, 1uF, its impedance is Xc = 1/(2*pi*f*C.
/cfs-file/__key/communityserver-discussions-components-files/6/OPA1641-E2E-09102020A.TSC
Best,
Raymond
Hi Alassane,
Would you prefer this way? The cutoff frequency is approx. 3.4MHz.
Please let me know if you have any additional questions.
/cfs-file/__key/communityserver-discussions-components-files/6/OPA1641-E2E-09102020B.TSC
Best,
Raymond
Hi Alassane,
Below is the cutoff frequency plot.
/cfs-file/__key/communityserver-discussions-components-files/6/OPA1641-E2E-BW-0911020.TSC
(I accidentally submitted something while I am uploading the image, here are the rest).
Q. Is there a way to easily, as in ltspice, to calculate the input and output impedance of this circuit?
Enclosed is the Tina simulation of input and output impedance of the circuit. I am unable to assist you with LTSpice due to license agreement, but the measurement approach is very similar.
BTW, the dB to output impedance conversion is 10^(dB/20) at a given frequency, since nominal current is injected at the output, the output gain in dB response to Vout/I_inject, which is output impedance vs. frequency.
/cfs-file/__key/communityserver-discussions-components-files/6/OPA1641-Input-Impedance-09112020.TSC
/cfs-file/__key/communityserver-discussions-components-files/6/OPA1641-Output-Impedance-09112020.TSC
If you have additional questions, please let us know.
Best,
Raymond
Hi Alassane,
You gave me non-inverting op amp configuration. The Gain Bandwidth Product (GBP or GBW) is 11MHz at Gain=1. 1nf is used for compensate the 2nd pole found at higher frequency.
If you talking about the inverting op amp circuit below, then your formula is correct. Hope this helps.
/cfs-file/__key/communityserver-discussions-components-files/6/OPA1641-Inverting-Config-0911020.TSC
Best,
Raymond
