TLV320AIC10: DAC's difference output signal in RESET is enable.

teritama

Expert 1690 points

Part Number: TLV320AIC10

Hi team,

When do operation ① to ③, OUTP and OUTM voltage change like figure 1 wave.

And this level change is looked DC component from output stage circuit.

①Make RESET pin Hi, device operate normal mode.

②Initialize control register (Reggister1=0x00, Register2=0x0A, Register3=0x01, Register4=0x00)

③Reset the device, RESET pin is Low.

About 30sec later, OUTM and OUTP voltage change.

Our customer tested this operation on four device with the circuit configuration on figure2.

This voltage fluctuation occurred on all device.

Even when MCLK and DIN input no signal, this voltage fluctuation occurred .

I want to know what reason or mechanism this voltage fluctuation occurred and TI's view.

This voltage fluctuation varies in the range of 196.0mVpp to 73.0mVpp.

Best regards

teritama

over 4 years ago

0 Aaron Estrada over 4 years ago

TI__Mastermind 22950 points

Hello Teritama,

How long is the reset pin being held LOW? Data sheet requires LOW pulse to be at least 6 MCLK periods long. Can you please provide any scope shots of the RESET function?

Regards,

Aaron

0 teritama over 4 years ago in reply to Aaron Estrada

Expert 1690 points

Hi Aaron,

RESET pin keep Low state after ③ operation.

So Low signal is over 6 MCLK periods long.

Regards,

teritama

0 teritama over 4 years ago in reply to teritama

Expert 1690 points

Hi Aaron,

Is it OK to understand the that cause of voltage fluctuation is RESET pin function?

I think keep RESET pin Low is one of cause after ③ operation.

Do you recommend RESET pin keep Low?

Regards,

teritama

0 Aaron Estrada over 4 years ago in reply to teritama

TI__Mastermind 22950 points

Hello Teritama,

It seems like the device is getting configured prior to applying the low going RESET pulse. RESET pulse should be low going and last at lease 6 MCLK cycles and then brought back HI. The device should be reset to default state and may be configured.

Regards,

Aaron

0 teritama over 4 years ago in reply to Aaron Estrada

Expert 1690 points

Hi Aaron,

Thank you for reply.

>RESET pulse should be low going and last at lease 6 MCLK cycles and then brought back HI.

⇒This means RESET pulse should be brought back Hi after at least 6MCLK(here (1/36.846MHz)*6=0.16ns)?

And It is possible "cause of voltage fluctuation is device configured unknown setting by that RESET pulse is not Hi".

Is the above recognition correct?

best regards

teritama

0 Aaron Estrada over 4 years ago in reply to teritama

TI__Mastermind 22950 points

Hello Teritama,

I believe your understanding is correct. RESET should be brought back HI after at least 6MCLK cycles have completed. This would ensure a proper RESET was sent to the device. Step two should come after RESET is back HI. Remember that the RESET is an active LOW. So RESET is enabled when it is brought LOW.

I cannot say for sure that this is the cause of the output voltage fluctuations but it seems like the device is not getting properly RESET>

Regards,

Aaron

0 teritama over 4 years ago in reply to Aaron Estrada

Expert 1690 points

Hi Aaron

Thank you reply.

I understood cause of the fluctuations.

Let me ask you another question.

Can you explain operation of OUTP and OUTM while RESET pin is Low?

Or this operation is not guaranteed?

Best regards

teritama

0 Aaron Estrada over 4 years ago in reply to teritama

TI__Mastermind 22950 points

Hello Teritama,

This is an older device and unfortunately, I am not sure the state the outputs are in during reset but I would expect no operation from the device during the reset state.

Regards,

Aaron

0 teritama over 4 years ago in reply to Aaron Estrada

Expert 1690 points

Hi Aaron,

Thank you for your support.

I understood.

Best regards

teritama

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TLV320AIC10: DAC's difference output signal in RESET is enable.