Other Parts Discussed in Thread: AM5718,
Hello,
We are designing an Audio processing module using the Audio CODEC chip TLV320AIC3268. The host for the Audio CODEC chip is TI's AM5718 Processor. The application is to have single channel Audio (Voice band) input and output (mono mode). We are having the below queries regarding the digital audio interface b/w the mentioned IC's.
1. In mono mode, the Fs of ADC & DAC need to be set to 8KHz. It is understood that 8KHz sampling frequency can be derived from MCLK and the NDAC, MDAC and DOSR dividers settings. In McASP application guide (SPRACK0: Section 2.3), it is mentioned that the word clock (WCLK / FSYNC) should have the same frequency as ADC/DAC sampling frequency (The frame sync clocks run at the audio stream’s sample rate ). Which means WCLK should be set to 8KHz. I have seen in the below ticket raised in forum with 8KHz mono mode settings: MCLK = 12.288 MHz, BCLK = 3.072 MHz, WCLK = 48 kHz (slave). Here WCLK is not set at 8KHz sampling rate. If WCLK is set at 8KHz, BCLK also will vary and ultimately MCLK should be adjusted accordingly. Need clarification regarding this doubt.
2. One more doubt is basic to McASP interface. The host Processor is having multiple number of AXR[n] pins up to 16, down to 4. What is the exact purpose of having more number of data lines within one port? If we are using the 2 ASI ports of Audio CODEC IC and if we are interfacing to a single McASP port of host Processor, only four lines will be used (2 TX & 2 RX). What if I am using host McASP with 16 data lines? Remaining 12 lines will be floated. Is McASP interface with 16 data lines is expecting 8 TX & 8 RX lines from external Audio chip?
Regards
Hafiz
