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TPA3110D2: GAIN0 and GAIN1 slew rates

Part Number: TPA3110D2

Dear All,

In TPA3110D2 spec sheet, there is a description of necessary slew rate of gain setting pins as below:

9.3.2 Gain Setting Via GAIN0 And GAIN1 Inputs
The gain of the TPA3110D2 is set by two input terminals, GAIN0 and GAIN1. The voltage slew rate of these gain terminals, along with terminals 1 and 14, must be restricted to no more than 10V/ms. For higher slew rates, use a 100kΩ resistor in series with the terminals.

Please let me know why digital setting pins of GAIN0 and GAIN1 has slew rate indication?
How does rising-up time affect the gain setting function?

Best Regards,
Andy

  • Andy,

    When high slew rate show up on these pins, it may will make some false trigger of internal circuit.  This fault trigger could be avoided by simply add 100Kohm resistor.

    Dylan

  • Hi Dylan,

    Thank you for good info.
    So I guess that is indicated for preventing a pop noise caused by over shoot of false trigger.
    Then it does not matter if that pop noise does not matter for product quality or even it does not appear if gain setting is fixed on PCB.

    In sample circuit, gain pins are tied to GND without resistors. But I see no sample that ties any of them to the Vcc directly.
    Is it good if I designed PCB pattern of GAIN0 to GND and GAIN1 to AVCC directly without any resistor?

    Andy

  • Hi Andy,

    I think you misunderstand me in last post. This slew rate limit is not for pop noise, it is for false trigger of internal circuit. When false trigger happen, device will behave with strange behavior. Please do follow TI suggestion to add 100Kohm pull up resistor when these pins are connected to VCC.  If these pin just connected to GND, that is fine.

    Dylan

  • Thanks Dylan. I see it is related to internal curcuit behavior. I keep 100Kohm pull up.