Connecting (2) analog phones using (2) AIC3254s with echo-cancelation

Dennis Bennett

Other Parts Discussed in Thread: PUREPATHSTUDIO

I am wanting to connect 2 headset phones (via analog 3.5mm jacks) and perform echo-cancelation on one of the headsets phones. I need some advice on this connection.

1) Purepath “AIC3254 Acoustic Echo Cancellation (AEC)” app note says that “MonoI2S_In_AEC” and “MonoI2S_Out” components are required. Because of this, I will need to connect the (2) AIC3254 as shown in Figure 2 below. Does this look correct?

2) After I cross-connect DOut and Din, (via ribbon-cable) to/from J14 for this connection, does the slave and master use BClk and WClk provided (by the master) for this transfer?

Thank you,

-Dennis

over 14 years ago

0 Don Dapkus over 14 years ago

TI__Guru**** 189401 points

Dennis,

That looks correct...

-d2

0 Dennis Bennett over 14 years ago in reply to Don Dapkus

Prodigy 150 points

Hi Don,

Thanks for the help. It is working as shown, but why is the sound quality so poor when I use a 8kHz sample clock. The config file I am using is attached. I have a 4.096Mhz MCLK, (using the USBMODEVMxxx_8KHZ.Bin)

My goal is to use the AEC using the PurePathStudio "AIC3254_AEC_32_1" example process flow, which only supports the 8kHz.

Fullscreen 3364.USB_8kHz.cfg.txt Download

###############################################
#
# For use with the following firmware image:
# ..\image\USBMODEVM0202_8KHZ.BIN
#
# This sets BLK AND WCLK AS outputs
#
# This script configures both ADC and DAC
# channels for line-in and headphone
# monitoring.
#
# An analog loopback test can be performed by
# connecting a 1/8" male to male cable from
# J10 (Headphone Test) to J1 (IN1).
#
###############################################



###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################



###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 4.096 MHz,
# BLCK = 512 kHz, WCLK = 8kHz
###############################################
#
# Select Page 0
w 30 00 00
#-----------------------------
# PLL_clkin = MCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=24(x18) 8, D=0000
w 30 04 03 91 18 00 00
#-------------------------
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 768, DOSR(9*8)
w 30 0D 03 00
#-------------------------
# NADC = 8, MADC = 12, dividers powered on
w 30 12 88 8c
#
# AOSR = 128
w 30 14 80
#---------------------
#   OR
#-------------------------
# NADC = 2, MADC = 48, dividers powered on
#w 30 12 82 B0
#
# AOSR = 128
#w 30 14 80
#---------------------


# BCLK frequency is generated from DAC_MOD_CLK
# and N = 12 (0x0c)...so DAC_MOD_CLK/12 = 6144/12 = 512
w 30 1D 01 8C
#
# Set BCLK and WCLK as outputs
w 30 1B 0C
#
#
###############################################
# Configure Power Supplies
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the input power-up time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#

###############################################
#
###############################################
# Configure Processing Blocks
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P2 and PRB_R2 selected
w 30 3C 02 02
#
###############################################



###############################################
# Configure ADC Channel
###############################################
#
# Select Page 1
w 30 00 01
#
# Route IN1L to LEFT_P with 20K input impedance
w 30 34 80
#
# Route CM1L to LEFT_M with 20K input impedance
w 30 36 80
#
# Route IN1R to RIGHT_P with 20K input impedance
w 30 37 80
#
# Route CM1R to RIGHT_M with 20K input impedance
w 30 39 80
#
# Unmute Left MICPGA, Gain selection of 6dB to
# make channel gain 0dB, since 20K input
# impedance is used single ended
w 30 3b 0c
#
# Unmute Right MICPGA, Gain selection of 6dB to
# make channel gain 0dB, since 20K input
# impedance is used single ended
w 30 3c 0c
#
# Select Page 0
w 30 00 00
#
# Power up LADC/RADC
w 30 51 c0
#
# Unmute LADC/RADC
w 30 52 00
#
###############################################



###############################################
# Configure DAC Channel
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop: 5 time constants, 6k resistance
w 30 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Power up HPL/HPR
w 30 09 30
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################

I load this file into both units, (on the slave, I use the CS software to change the BCLK and WCLK to inputs).

Does this config look ok? What would explain the poor sound quality?

Thank you,

-Dennis

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Connecting (2) analog phones using (2) AIC3254s with echo-cancelation