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DIX4192-Q1: Questions

user6491608
Prodigy 60 points
Part Number: DIX4192-Q1
Other Parts Discussed in Thread: DIX4192

Hi,TI:

I use DIX4192 for I2S ⇒ S/PDIF conversion(Port A⇒DIT).I have some questions.

Q1  when Port B and DIR block power off,How much supply current?fs=44.1kHz

Q2  Do we have to connect pull-up and pull-down resisters to the SPI lines? or are they already connected them internally?

Q3  How to process Unused PIN 12/13/23/34/35/36/45/46/47/48

  • 0
    TI__Mastermind 23050 points

    Hi,

    While the supply current will definitely decrease with various blocks powered off, we only spec with all blocks on or off so I will need to measure this and get back to you!

    Pullup resistors are not generally necessary for SPI buses because they are actively driven with a totem-pole style drive circuit. You may just want to verify this on your host processor though.

    All of the unused pins you mentioned can be left floating.

  • 0 in reply to Zak Kaye
    Prodigy 60 points

    Hi

    Thank you for your help.I understand.

    there are two other questions.

    Q1 How long can the RST be rised afer Power ON?

    Q2 Is there any problom for a long time for tr/tf of MCLK?

  • 0 in reply to user6491608
    TI__Mastermind 23050 points

    Hi,

    I'm not sure I understand your question. Reset should be released after the supplies have settled and then you should wait at least 500us before any I2C or SPI transactions are attempted.

    It is best to keep the rise and fall times of MCLK low if this is used as the reference clock because long rise and fall times result in increased jitter and this can degrade the quality of the signal. If the rise and fall times are too long the device may not be able to lock reliably.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 60 points

    Hi,

    I want to konw the timing requirements between VDD and RST.

    How to quantitavely evaluate the tr/tf ,are there any requirements? 

    thanks.

  • 0 in reply to user6491608
    TI__Mastermind 23050 points

    Hi,

    There is not a timing requirement between VDD and RST, it is just recommended not to release RST until VDD has settled to ensure the device initializes in the default state. Since you are using SPI alternatively you can issue a software reset after startup to ensure this.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 60 points

    Hi,Zak

    About the MCLK,how to quantitavely evaluate the tr/tf ,are there any requirements?

    Does MCLK need to synchronized with the BCK?

    Best Regards

  • 0 in reply to Zak Kaye
    Prodigy 60 points

    Hi

    About 75-Ω transformer-coupled line driver interface.What are the pros and cons of the two connections in the file.

    unbalance.xlsx