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PCM1860-Q1: PCM1860-Q1 Power up sequence

user6388211
Prodigy 250 points
Part Number: PCM1860-Q1

Please tell me about the start and end sequences.

I am thinking of starting and terminating by Power-On Reset.

According to the data sheet P.81, after the voltage value of the internal LDO is 1.5V and the [LDO_GOOD] flag is set to High, the clock is digitally reset with 16 pulses.

Please tell me the threshold voltage of Power-On reset.

DVDD: __V

AVDD: __V

IO VDD: __V

How many seconds below the threshold to reset?

time:

[As a condition]

-Do not input MCLK and use the internal PLL from BCK. 

-The INT pin is pulled down with 10kΩ.

  • 0
    TI__Mastermind 23050 points

    Hi,

    I'm not sure where the exact POR threshold is set but I would suggest using the minimum recommended operating voltage as a conservative estimate.

    Is this intended for power savings when the device is not used or because of a change in HW settings like the filter type requiring a reset? Note that the device can enter low power mode just by disabling the clocks and pulling INT high.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 250 points

    Hello, Zak-san

    Power saving is not the purpose.

    When the power supply voltage is set to On → Off → On, I am concerned about the threshold voltage because I want to start after resetting.

    I understand that the internal LDO voltage is reset at 1.5V.

    Does the internal LDO output 1.8V have the same voltage 1.8V output regardless of whether IO VDD is 3.3V or 1.8V?

    I would like to know the relationship between the external power supply (DVDD / IO VDD / A VDD) and the output voltage of the internal LDO.

  • 0 in reply to user6388211
    TI__Mastermind 23050 points

    Hi,

    The internal LDO is always 1.8V. It can be bypassed if you are using 1.8V IOVDD though by connecting an external 1.8V supply to it, but only if IOVDD is also 1.8V. 

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 250 points

    Hello,

    Thank you for your reply. OK.

    I have listed the parts that I would like you to tell me at the timing in the file. Can you check the attached file?

  • 0 in reply to user6388211
    TI__Mastermind 23050 points

    Hi,

    Unfortunately I don't have this level of timing information for this family. The OSC clock and digital reset are internal signals that cannot be measured and will stay active as long as the device has power.

    The LDO rise and fall time should track IOVDD.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 250 points

    Hello,

    OK.

    Let me check 3 points.

    1. I understand that the Power-on reset of PCM1860-Q1 is controlled by [Digital reset] from Fig.69. Is it correct?

    2. It seems that [Digital reset] is canceled when [OSC Clock] is 16 clocks. Is it okay to understand that [Digital reset] is applied when [OSC Clock] stops?

    3. If you make an SCK with a PLL inside the BCK instead of inputting from the OSC / SCK, is it okay to understand that [OSC clock] starts after the BCK is input?

  • 0 in reply to user6388211
    TI__Mastermind 23050 points

    Hi,

    The digital reset is based on an internal oscillator once the power rails are provided, not an externally provided clock. Once you power up without clocks the device will remain in the "wait clock stable" state which is the clock detection portion of the diagram you have attached. 

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 250 points

    What should be the power on / off timing when operating with the internal PLL without using MCK (XI or SCKI)?

    Power On-> BCK in (PLL on)-> BCK off (PLL off)-> Power Off

    Is it okay?

    Is there anything I should be careful about when turning the power on / off?

  • 0 in reply to user6388211
    TI__Mastermind 23050 points

    Hi,

    Yes it is generally best not to apply signals to unpowered inputs so if you can follow that sequence that would be ideal.

    Best,

    Zak