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Original question:

PCM6340-Q1: HVDD shutdown sequence

PCM6340-Q1: VREF_QCHG, DREG_KA_TIME

Shinji Tsuji
Genius 12338 points
Part Number: PCM6340-Q1

Hi team,

Could you advice the guide line of VREF_QCHG and DREG_KA_TIME setting?

1. VREF_QCHG setting

If I use larger capacitor than 1uF for VREF, how should I chose this setting? Any negative impact if I chose default 3.5ms setting while selective much higher capacitor than 1uF?

2. DREG_KA_TIME setting

What is the purpose of this feature?

regards,

  • 0
    TI__Mastermind 23050 points

    Hi Shinji-san,

    The VREF charge time plays a role in the startup timing and when data is output on the bus. If a larger value bypass capacitor is used you should change the VREF startup timing to avoid the first few data samples being inaccurate and choose the timing based on how much larger you make the cap. If you use 2uF, then set the time to 10ms. If you use 10uF, then set the time to 50ms.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Genius 12338 points

    What is the purpose of setting DREG_KA_TIME?

    regards,

  • 0 in reply to Shinji Tsuji
    TI__Mastermind 23050 points

    Hi Shinji-san,

    The DREG_KA_TIME is described in register 0c05 and sets how long the DREG will remain powered after a shutdown grom SHDNz pin is asserted. It's intended for a smooth powerdown but can be disabled if preferred. 

    The functionality is described in more detail in this thread: 

    Though this is a different family of devices, the DREG behavior is the same between the two!

    Best,

    Zak