TLV320DAC3120: WithOut MCLK

Hi,

It was confirmed with DOSR = 32.

Best regards.

Hi,

Thank you for your response. Does it mean that the problem was solved with DOSR = 32?

I think I made a mistake on my previous suggestion and MDC should be 1 to reach 8K sampling rate with DOSR = 32.

fs = BCLK / (NDC x MDC x DOSR) = 256KHz / 32 = 8KHz.

Best regards,
Luis Fernando Rodríguez S.

Hi,

It's a mistake in my question.
I repeat.
I set CODEC_CLKIN to BCLK = 256kHz, NDC = 1, MDC = 1, DOSR_LSB = 32 , but no speaker output.

Best regards.

Hi,

Thank you for your clarification.

Could you provide the entire registers configuration and the circuit schematic in order to have a better approach to this issue?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Hi

A list of register set values and a schematic are attached.

Best regards,
T.Konno.DAC register.xlsxTLV320DAC3120_SCH.pdf

Hi

A list of register set values and a schematic are attached.
I will send you the list again.

Best regards,
T.Konno.DAC register.pdf

Hi

I'm sorry there was a mistake in the comment on the schematic.
Correctly in clock frequency, with MCLK not connected
I2S3_SCK = 256kHz
I2S3_WS = 8kHz

Best regards,
T.Konno.

Hi, T.Konno,

Thank you for the information you provided.

I actually noticed that page 0 / register 4 is configured as 0x0D. This correctly takes the BCLK as CODEC_CLKIN, but this value also sets DIN as the PLL clock. So, all the data you use for DIN will be ignored.

Could you modify this value from 0x0D to 0x01?

Please let me know if you still have issues with it.

Best regards,
Luis Fernando Rodríguez S.

Hi

Thank you for the verification.

Even if I change it to 0x01, there is no sound.

When I tried using PLL with 0x0D, there was a sound.
But it seems that there are many jitters.
Is it because the frequency limit has been exceeded? (BCLK = 256kHz.)

Best regards,
T.Konno.