TLV320DAC3100: Register settings for 4MHz MCLK

Hi John,

we have received your questions, we will check with the team and feedback to you soon.

Br,

Wenbin

Hi John,

as the 44.118 is not the exact right value, please use J=5,D=9976 instead, and keep other value the same.

in this case, you can get 44.1kHz.

Br,

Wenbin

Thanks for your help, but in the datasheet there is a a condition mentioned that when PLL is enabled and D is not zero, then PLL_CLKIN/P must be between 10MHz and 20MHz.  (In my case, this would be 4MHz?).  Does this matter?

J.

Hi John,

Yes, my suggestion can't meet the requirement (PLL is enabled and D is not zero, then PLL_CLKIN/P must be between 10MHz and 20MHz).

so in fact,  there is no available settings for 4MHz clk input and 44.1k sample rate.

so please try to change the input clk to a proper clk.

or , if alternative you can use 48kHz sample rate, maybe you can use the following setting to have a try. but it will have some limitations, Interpolation Filter A can't be used. (PRB_P1~P6;P23~P25 can't be used). because DOSR is 100, it can't meet Filter A's requirement.

P=1, R=4, J=6, D=0, MDAC = 5, NDAC = 4, DOSR = 100(only use Interpolation Filter B or C), input clk 4MHz, 48kHz sample rate.

Br，

Wenbin

ok - thanks for clarifying.  I appreciate your help.

I will try the 48kHz solution or an alternative clock.

J.