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PCM1865: PCM1865 false antialiasing when changing fs in runtime

user3680879
Intellectual 390 points
Part Number: PCM1865

Hi, Team,

We need to change the FS according to the configuration in runtime , but   found there have large opportunity the false antialiasing responce ,when change from 48k to 96k, or 96k to 192k.  The amplitude responce curve also changed with the FS, became much dip in the edge and not flat as normal run.  The PLL config is as your datasheet.

Could you give some advice on the issuse?

Best Regards,

James

  • 0
    Intellectual 390 points

    Hi, Team,

    When changing Fs, We just re-write the PLL  and some clock related reg and left others unchanged, as below for 48k:

    #Select Page 0
    w 94 00 00
    #Master Mode, PLL as source
    w 94 20 3E
    #System Clock Dividers
    w 94 21 03
    w 94 22 07
    w 94 23 0F
    #Audio Clock Dividers
    w 94 25 07
    w 94 26 07
    w 94 27 1F
    #PLL Parameters
    w 94 29 01
    w 94 2A 00
    w 94 2B 08
    w 94 2C 80
    w 94 2D 07
    #PLL Configuration and Enable
    w 94 28 01

    Anything missing?

    Best Regards,

    James

  • 0 in reply to user3680879
    TI__Mastermind 23050 points

    H James,

    Please give me some time to review your settings and get back to you. Can you elaborate on the problem that you are seeing? I don't know what is meant by a false anti-aliasing response. Any data you can share from your testing would be helpful for understanding the issue you are facing.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Intellectual 390 points

    Hi,Zak Kaye,

    Many Thanks!

    We are using the codec as the adc for the dual IQ signal recieving. The phasing were correct  when just running in one of the Fs as 48k ,96k or 192k at power on. But when we change the Fs  in runtime, there have chance to lost the phasing ,resulting the aliasing signal been detected after doing the FFT. Or maybe the digital filter Iinside the codec cracked in that case? The ADC is running in master mode and we just stop the i2s DMA of the MCU and change the clock related reg as above. 

    Could you help to evaluate the issue in your EVM board?  Is there any  command could reset the ADC in runtime?  

    Best Regards,

    James

  • 0 in reply to user3680879
    TI__Mastermind 23050 points

    Hi James,

    Are you using a non-audio clock for master mode operation? Otherwise, you should not need to change the PLL settings if you are using the autodetect clocking scheme and the MCLK is one of the supported multiples for autoclock generation (256*fs, 384*fs, 512*fs).

    I also think there are some errors in your PLL and divider configuration. How exactly these should be set depends on what your master clock is. I would recommend using the PLL calculation tool found here: 

    There is a configuration script tab that can be copied once you have verified your configuration is valid.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Intellectual 390 points

    Hi,Zak,

    Many Thanks!

    We use 24Mhz as the master clock. You suggested not to re-config the PLL again and just modify the divider reg for changing Fs? The setting of the PLL and  divider reg are followng  your former  document: PLL Tool PCM186x and should be correct?

    Your file is PCM186xMixerCoefficientwithmacro ?

    We suppose that the phasing of the L/R channel were changed sometimes when changing the Fs on the fly .

    Is there any command could reset the phasing?

    Best Regards,

    James

  • 0 in reply to user3680879
    TI__Mastermind 23050 points

    Hey James,

    Yes sorry I must have linked the wrong file, the PLL tool is the correct one. It doesn't look like your divider settings match the required clock settings though. Here is the script I generate:

    #Select Page 0
    w 94 00 00
    #Master Mode, PLL as source
    w 94 20 3E
    #System Clock Dividers
    w 94 21 07
    w 94 22 07
    w 94 23 0F
    #Audio Clock Dividers
    w 94 25 07
    w 94 26 00
    w 94 27 FF
    #PLL Parameters
    w 94 29 01
    w 94 2A 00
    w 94 2B 08
    w 94 2C 80
    w 94 2D 07
    #PLL Configuration and Enable

    w 94 28 01

    I would recommend not changing the PLL values and only the dividers when switching sample rates. Alternatively, you can set CLKDET_EN to 1 for the atuoclock scheme and then you only need to configure registers 0x26 and 0x27.

  • 0 in reply to Zak Kaye
    Intellectual 390 points

    Hi,Zak,

    Many Thanks!

    1. I checked your script with mine, the only different is from my setting of parameter as below:

    System Clock (SCK) 128 ×Fs
    Bit Clock (BCK) 32 ×Fs
    Word Clock (LRCK) 1 ×Fs

    It seems also an acceptable result.

    2. You means it could set the  CLKDET_EN to 1 even if running on non_audio frequency MCLK input (24Mhz) with proper PLL configuration?  If so , that is great.

    3. How to soft restart the codec when false detected?

    4. Is there any safty order to set the reg? PLL first or the FMT (reg 0x0B)?

    Best Regards,

    James

  • 0 in reply to user3680879
    TI__Mastermind 23050 points

    Hey James,

    I assumed that your clock was actually 24.576MHz but you're correct if you are not using a standard audio rate clock you will have to manually configure the PLL. Pulling the INT pin low will force the device into a low power state so you might try this when the issue is detected. 

    I would recommend powering down the PLL prior to changing the settings to ensure a smooth transition to the new sample rate and avoid any phase issues. I would recommend setting the PLL prior to the FMT.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Intellectual 390 points

    Hi,Zak,

    Many Thanks!

    Great help! I am trying.

    Best Regards and Nice weekend,

    James