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PCM4220: BCK Master duty cycle at 192K

SeattleEE
Intellectual 480 points
Part Number: PCM4220

Hi, I'm using the PCM4220 in master mode. Input clock is 50%, 24.576M. In 48K and 96K mode, the output bit clock is 50%, but in 192K mode, the output clock BCK is 69% duty cycle at 12.29 MHz. This is confirmed directly at the pin with all loads removed (jumper is on board right at the pin). The data sheet is really clear that the BCK in "all data formats" should have a duty cycle of 45 to 55% (page 5). With duty cycle at 69% and tdo of 10 nS, it's making data setup very difficult in other parts of the board.

Is this 69% duty cycle BCK expected for 192k?

Some settings: FMT0=1, FMT1=0, OWL0 = OWL1 = 0, SUB0 = SUB1 = 0, DF = 0, HPFDx = 0

Thanks

  • 0
    TI__Mastermind 23050 points

    Hi,

    I would not expect a 69% duty cycle BCK. Can you please confirm the state of the FS pins? These should be set to PCM quad speed for 192kHz operation, so FS1 should be HI and FS0 should be LO. Additionally, there are restrictions on the allowable system clock in master mode depending on which sample mode is used as given in table 1. When operating in PCM quad speed the required master clock is 64*fs, or 12.288MHz in your case. 24.576MHz is never a valid MCLK frequency.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Intellectual 480 points

    Hi Zak, sorry, there's an external /2, so the MCLK into the PCM4220 is 12.28 MHz and the BCLK out is 12.28 MHz. I've attached the the scope plot (scope BW is 300 MHz, 10:1 probes), plot looks similar with BCLK completely unloaded). The phase relationship is always the same. Finally, amplitudes on both are ~3.3Vpp (100mV/div is really 1V/div, 200mV/div is really 2V/div)

    I've confirmed FS1 (pin 20) = 1 and FS0 (pin 19) = 0. So, it sounds like at 192k the duty cycle should absolutely be between 45 and 55% at 192 KHz. If you can confirm, I'll keep searching. Please let me know if you think of anything else that might cause this. Thanks

  • 0 in reply to SeattleEE
    TI__Mastermind 23050 points

    Hi,

    Thank you for clarifying. I wouldn't expect BCLK to have a duty cycle outside of spec like this, but let me see if I can reproduce this on our EVM. I won't have lab access until next week but I should be able to get back to you on Monday with confirmation.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Intellectual 480 points

    Hi Zak, thanks for checking. It's on all boards and it's really hampering the board timing. So, if there's a setting that can get it back to the spec'd value it'd be great to learn. 

  • 0 in reply to SeattleEE
    TI__Mastermind 23050 points

    Hi,

    I was able to test this in the lab on an EVM and I actually see the same duty cycle behavior that you do t 192kHz master mode. I tried sourcing the MCLK from an onboard crystal as well as from an AP and there was no change. I believe this is actually characteristic of the device now and that at higher sample rates the duty cycle is not within the 45-55% limit. Since this clock division happens internally unfortunately I don't think there is much you could do to improve it outside of running at slower sample rates.

    Best,

    Zak