DIX4192: DIX4192 Interfacing

Hi James,

We're not familiar with the Brooklyn II CPU and what the overall application requirements are which would dictate if an ASRC function is required or not.

On the transmit side out of the CPU (Bus master)-> to DIX4192-> to AES stream does not require any ASRC operations provided the downstream AES is meant to run at the same sampling rate as the CPU ASI bus.

On the receive side from the incoming AES stream -> to DIX4192 -> to I2S to CPU (Bus master), an ASRC will be likely required since the receiver module in the DIX device is typically used to drive the outgoing I2S stream as the ASI master and it's very unlikely that the CPU master BCLK/WCLK signals will match properly with the AES stream timing and sampling rates.  We believe a solution here to still operate the DIX in slave move in this configuration would be to use the recovered MCLK from the DIR module in the DIX4192 as the master clock input to the CPU which then generates the master BCLK/WCLK signals to the DIX4192 to clock out data.  This way the recovered MCLK clock from the incoming AES stream will still synchronize the CPU ASI bus to the data.

Hey Collin,

Thanks for your answer, that pretty much answers my question. I appreciate your help! I think I will need an ASRC on the receive side. So could I use the SRC4382 or the SRC4392 instead of the DIX4192, since they already have the ASRC built into the chip as well as the DIR and DIT functions?

Thanks in Advance,

Jim Berry

Hi Jim,

You're correct and you could use the additional functionality in the SRC to adjust the sampling rate on the S/PDIF output from the DIT module in the SRC which would also not be possible with the DIX4192.

Hi Collin,

That is good news, and it answers all my questions! Thank you very much!!!

Best Regards,

Jim Berry