Hello,
we want to use 5 x PCM1840 ADCs on a board - all with the TDM audio interface format.
Our plan is:
- The first ADC in master mode, this ADC drives the signals FSYNC and BCLK for the other 4 ADCs in slave mode.
- We use a 12,288 MHz clock oscillator for the first ADC in master mode and want to use a 48 kHz sampling rate.
- We use the TDM audio interface format and each ADC feeds the output signal SDOUT direct to a FPGA.
- The FPGA can reset all ADCs via the common reset line that is routed to all 5 ADCs.
Our questions:
- Does this concept fit or what should be changed?
- Is it correct to drive MD0 = low for 256 x fs?
- With what frequency the ADC will drive the BCLK? (12,288 MHz like the clock for the first ADC in master mode or any other frequency?)
- What power up behavior the 5 PCM1840 will show, when the first ADC starts to drive the signals FSYNC and BCLK and not all 4 ADCs in slave mode are out of the shutdown yet?
- Only the output data signal SDOUT is incorrect and will be correct by the next FSYNC after the ADC is out of the shutdown?
- What effects or side effects can occur?
