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PCM3168A: TDM8 output doesn't lock to the host frame clock

Part Number: PCM3168A
Other Parts Discussed in Thread: PCM3168

We are using the codec in a slave mode TDM8 512xFs, 48KHz, master clock is 24.576MHz.

LRCLK and BCLK are provided by a DSP. Master clocks to the codec and DSP are coming from the same source.

Both codec and DSP are configured for I2S TDM8 audio format.

The TDM8 output of a codec doesn't lock to the start of the LRCLK frame. Instead it locks at occasional place.

If I restart DSP, TDM8 out locks at a different place, but still not to the start of a LRCLK frame.

What could be a reason for it?

Another question. In one of the codecs (we use four) we need to use only AD, but no DA.

Nevertheless there is no TDM8 from output from this codec if DA audio clocks are not connected.

Is that how it's supposed to be?

Thank you,


  • Hi Gennady,

    Do you have a timing diagram for the DSP that you could share so we can confirm the format settings? Are you using the PCM3168A in HW or SW controlled mode? If you could share your configuration settings this would also be helpful.

    The ADC and DAC sections can be run independently and it is not necessary to supply the DAC clocks to run the ADC, but an SCKI is always required.



  • Hi Zak,

    Thank you for your reply.

    The codec is used in a software controlled mode.

    Please find attached an excerpt from the ADAU1467 datasheet and codecs' configuration.

    BTW, we used PCM3168 before with other Sigma DSPs and XMOS processors, but never experienced this issue.

    But I think we used it in I2S mode, not TDM8.

    Also we tried to use the codec in ADC only, but didn't see any TDM output until DAC audio clocks were connected.

    I believe DACs were not disabled, could it make a difference?

    Thank you again,



    /* 512fs, system clock 24,576 MHz, sampling clock 48 KHz, TDM8 I2S audio format */
    uint8_t codec_set_array[31] =
      0xC1,   // 64 dac_resets_sampling
    		  // MRST(7)   - 1 - normal operation (default)
    		  // SRST(6)   - 1 - system reset ADC, DAC - normal operation (default)
    		  // SRDA[1:0] - 01 - DAC sampling mode select - single rate	
      0x86,   // 65 dac_ms_interf
    		  // PCMDA(7)   - 1 - DAC power save mode select (disable)
    		  // MSDA[2:0]  - 000 - DAC master/slave mode (slave - default)
    		  // FMTDA[3:0] - 0110 - DAC audio interface format (24 bit I2S TDM)
      0x0F,   // 66 dac_disable_rolloff
    		  // OPEGS[3:0] - 0000 - DAC operation control (normal operation)
    		  // FLT[3:0]   - 1111 - DAC digital filter roll-off (sharp roll-off - default)
      0x00,   // 67 dac_phase
    		  // REVDA[7:0]	- 00000000 - DAC output phase (normal output)
      0x00,   // 68 dac_soft_mute
    		  // MUTDA[7:0] - 00000000 - DAC soft mute control (disabled)
      0x00,   // 69 dac_zflag - read only
      0x00,   // 70 dac_att_mode_speed_deemph
    	      // ATMDDA(7)       - 0 - DAC attenuation mode (each channel with independent data)
              // ATSPDA(6)       - 0 - DAC attenuation speed (Nx2048/fs)	
    	      // DEMP[1:0] (5,4) - 00 - DAC digital de-emphasis function (disable)
    		  // AZR[2:0] (3..1) - 000 - DAC zero flag function select
    		  // ZREV (0)        - 0 - DAC zero flag polarity (default)
      0x00,   // r71 dac_att_common (n/a)
      0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // 72_79 dac_att[8] - 0xFF - default;
      0x00,   // 80 adc_sampling
    		  // SRAD[1:0] (1,0) - 00 - ADC sampling mode (auto - default)
      0x06,   // 81 adc_ms_interface
    		  // MSAD[2:0] (6..4)  - 000 - ADC master/slave select (slave)
    		  // FMTAD[2:0] (2..0) - 110 - ADC audio interface format (24-bit I2S TDM)
      0x00,   // 82 psave_hpf - hpf enabled
    		  // PSVAD[2:0] (6..4) - 000 - ADC power save (normal operation - default)
    		  // BYP[2:0] (2..0)   - 000 - ADC hpf bypass (hpf enabled, normal output)
      0x00,   // 83 adc_in_config
    		  // SEAD[6:1] (5..0) - 0x00 - ADC input configuration (differential)
      0x00,   // 84 adc_phase;
    		  // REVAD[6:1] (5..0) - 0x00 - ADC input phase (normal)
      0x00,   // 85 adc_soft_mute
    		  // MUTAD[5:0] (5..0) - 000000 - ADC soft mute enable (init disabled, set by profile)   
      0x00,   // 86 adc_ovf_flag;
    	      // read only
      0x00,   // 87 adc_att_mode_speed;
    	      // ATMAD (7)  - 0 - ADC attennuation mode (each channel independent data)
    	      // ATSPAD (6) - 0 - ADC attenuation speed (Nx2048/fs - default)
    	      // OVFR (0)   - 0 - ADC overflow flag polarity (default)
      0x00,   // r88 adc_att_common  
      215,215,215,215,215,215 //* 89_94_adc_att[6];

  • Hi Gennady,

    The code snippets are nice, but scope shots showing the actual bus transaction details are much easier to decipher.  Can you send the timing diagram Zak asked for perhaps with some screen shots of the I2S bus?

  • Hi Tom,

    The ADAU1467 timing timing specs are in the ADAU1463-1467_timing.pdf (right above the code snippet).

    And here is a scope screen shot showing where the TDM8 is located relatively to the frame clock.

    If I restart a host DSP, codec will resynchronize, but in most cases with TDM8 still not correctly locking to the LRCLK.    

  • Hi Gennady,

    The timing diagrams you provided only seem to apply to I2S and left or right justified modes, I don't see a depiction of the TDM timing anywhere. I think part of your issue might be that you are using I2S TDM mode, which basically just means that the data is offset by 1 and LRCK is 50% duty cycle. The FSYNC is NOT inverted in this mode though like it normally would be for I2S.

    Here is an example of the measurement setup in this config 

    If you don't want the 1 BCLK delay or a 50% duty cycle LRCK then you should operate the device in 24-bit left justified TDM mode instead and based on your scope shot it looks like this is the mode you should actually be using.

    I'm also not sure why you don't see data until the DAC clocks are provided as these are not required for ADC operation so I think this just hints at a configuration issue.