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Original question:

TLV320ADC5140: ENABLE DRE of TLV320ADC5140

TLV320ADC5140: Could not access DRE

Mochi
Genius 4175 points
Part Number: TLV320ADC5140


Hello,

Our customer is struggling to enable DRE too.

 

When look at your sample code in SBAA400, there is an order,

At first configuring DSP,

Then configuring each Ch parameter. 

 

w 98 00 00 # Goto Page 0

w 98 02 81 # Exit Sleep mode

d 10 # Wait for 16 ms

w 98 01 01 # Reset

w 98 6C 40 # Enable DRE in DSP_CFG1

w 98 3C 01 # Select DRE on Ch. 1 using CH1_CFG0

w 98 41 01 # Select DRE on Ch. 2 using CH2_CFG0

w 98 74 01 # Select DRE on Ch. 3 using CH3_CFG0

w 98 75 01 # Select DRE on Ch. 4 using CH4_CFG0

 

Should we follow this sequence?

Because our customer use opposite sequence, start from smaller number register 3C and then couldn't see DRE effect.

Is there any other restriction, like DRE registers access should be before Enable ASI and Power up ADC?

 

w 98 00 00 # Goto Page 0

w 98 07 30 # TDM Mode with 32 Bits/Channel

w 98 73 f0 # Enable Ch.1 - Ch.4

w 98 74 f0 # Enable ASI Output channels

w 98 75 e0 # Power up ADC     

 

Regards,

Mochizuki

  • 0
    TI__Mastermind 23050 points

    Hi Mochizuki-san,

    Part of the problem may be that if a reset is initiated the device goes back into sleep mode and so it is necessary to write to register 0x02 to wake the device up again. I would recommend setting all of the channel configuration and DRE settings before enabling the ASI output channels or powering up the ADCs.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 4175 points

    Hello Zak-san,

    Thank you for your prompt reply.

    Oh! it is kind of tricky part. SBAA400 sample code will not exit form Sleep mode after Reset command.

    So we should use following sequence, right? 

    w 98 00 00 # Goto Page 0

    d 10 # Wait for 16 ms

    w 98 01 01 # Reset

    w 98 02 81 # Exit Sleep mode

    w 98 6C 40 # Enable DRE in DSP_CFG1

     

    Our customer has additional questions.

    1. Can we change DRE parameter on the fly during enabling all ADC ch? Their post DSP will assert mute anyway.

    Or is it mandatory to set disable all of ADC ch for DRE parameter change to avoid malfunction DSP?

     

    1. Default value of DRE parameters on P5,P6,P7 are your recommended setting?

    Can we use those initial DRE settings for mass production product if we do not catch the artificial noise?

     

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 23050 points

    Hey Mochizuki-san,

    The DRE cannot be enabled on the fly, it is necessary to power down the ADC channel that you want to enable the DRE on first. The default values are our recommended settings that we believe should work for the majority of customers and we would suggest adjusting the max gain and DRE threshold first. I believe this will offer good performance, but if they do experience issues then it is possible to adjust the parameters.

    Best,

    Zak