Other Parts Discussed in Thread: STRIKE
Hi there.
Is there any information out there that relates the necessary clock requirements for the DAC_CLK and ADC_CLK with the amount of processing being done by the 3254 and the sample rate?
Am I correct in assuming that these clock speeds must be greater than the miniDSP_A/D_Cycle number * sample rate?
I see there are limits to the miniDSP clocks of around 55Mhz which therefore puts a limit on the processing the 3254 can do.
So would a higher sample processing rate of 88.2kHz or 96kHz be possible with a lower number of miniDSP cycles?
How can we strike the best balance between power consumption and processing?
Thanks in advance for your reply.
David