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TLV320AIC3101: Register setting

Kuramochi Tadahiko
Guru 28715 points
Part Number: TLV320AIC3101

Hi,

My customer is evaluating TLV320AIC3101 on their board, however, its ADC function and DAC function are not working.

MCLK and BCLK are common, and BCLK is 2.048MHz, Fs is 8kHz.

Could you check the following setting registers?

TLV320AIC3101 Registers.xlsx

Should we check anything else?

Best Regards,

Kuramochi

  • +1
    TI__Mastermind 22950 points

    Hello Kuramochi-san,

    Thanks for providing the register configuration but I have one questions first. Is this an I2C dump of the registers or a list of register writes that the customer is sending to the device?

    Assuming this is an I2C dump, here are my comments:

    - Both the left and right ADC are powered on and the PGA's are unmuted. This is good. I would expect there to be some data on DOUT. Is this not the case?

    - MIC2L is connected to the left ADC and MIC2R is connected to the right ADC. Are these the inputs the customer intends to use?

    - The PLL is enabled and configured for a 2.048MHz BCLK which is good. 

    - Both left and right DAC are powered on and unmuted and use the DAC_L3/R3 paths. This is fine. 

    - I see that the lineout drivers are powered down in registers 86 and 93. The driver power is controlled by Bit-D0 in these registers and should be set to 1. Please write 0x0B to registers 86 and 93. I know that Bit-D0 shows as a read only register but this is a typo and it is a read/write register. 

    - In register 102, please write 0xA2 to use BCLK as the primary clock source. 

    As noted above, I would expect DOUT to show data since the ADC's are powered on and the PGA's are unmuted. Can you please provide a scope capture of the ASI bus (BCLK, WCLK, DOUT)? It also looks like the customer is planning on using TDM and is configured for DSP mode. WCLK should be a bit wide pulse. 

    Regards,
    Aaron Estrada

  • 0
    Guru 28715 points

    Part Number: TLV320AIC3101

    Hi,

    My customer is evaluating TLV320AIC3101 on their board, however, its ADC function and DAC function are not working.

    MCLK and BCLK are common.

    In this case, is there any restriction regarding the start-up sequence(power supply, clock, setting register, removing reset)?

    Best Regards,

    Kuramochi

  • +1 in reply to Kuramochi Tadahiko
    TI__Mastermind 22950 points

    Hello Kuramochi-san,

    I believe this E2E post is related to another post by you. Is that correct? I have added the link below. 

    https://e2e.ti.com/support/audio/f/audio-forum/988119/tlv320aic3101-register-setting/3650165#3650165

    If so, I think it would be ideal to keep questions on the same topic in the same post if that is okay with you. I will make comments here but we can continue our discussion in the original post. 

    Regarding your the affect on the start up sequence, we ideally and obviously would like the device to be powered first with reset being held low until all supplies are fully powered up. The clock and register settings can affect whether data can be transmitted and received and this is mentioned in the original post. 

    Regards,

    Aaron Estrada