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SRC4392: How to control output data source

Part Number: SRC4392

Hello team,

I received some questions from my customer about the specification of SRC4392IPFBR. We would appreciate it if you could comment on the following questions:

Looking at " a[1:0] Port a Output Data Source " in Datasheet p52, are following understands correct?

Set to DIR: Sampling rate conversion feature is disabled and audio data for signal input to DIR is output from Port A.

Set to SRC: Sampling rate conversion feature is enabled and audio data is output from Port A for the signal selected in " SRCIS[1:0] SRC Input Data Source " as described in Datasheet p78

In Datasheet p72-75, they found the description " Receiver Block Start Clock". Can this clock be recognized as the clock that indicates the starting point of the data for the AES3 signal when the AES3 signal is entered?

Best Regards,

Ryotaro Fukui

  • Hi Ryotaro,

    The understanding for question 1 is correct. The SRC path need to be used if you want the output to run at a different sample rate, or if you want another device to act as the master of the ASI port. 

    For question 2 I believe this is a typo in the datasheet because the BLS and SYNC pins are part of the DIT, not the DIR. BLS can be used to indicate the starting point of the data for the transmitter, which may be helpful for downstream devices. This functionality is not necessary on the receive side for SRC4392.