I received some questions from my customer about the specification of SRC4392IPFBR. We would appreciate it if you could comment on the following questions:
Looking at " a[1:0] Port a Output Data Source " in Datasheet p52, are following understands correct?
Set to DIR: Sampling rate conversion feature is disabled and audio data for signal input to DIR is output from Port A.
Set to SRC: Sampling rate conversion feature is enabled and audio data is output from Port A for the signal selected in " SRCIS[1:0] SRC Input Data Source " as described in Datasheet p78
In Datasheet p72-75, they found the description " Receiver Block Start Clock". Can this clock be recognized as the clock that indicates the starting point of the data for the AES3 signal when the AES3 signal is entered?