Part Number: TLV320ADC5140
Hi Sir,
We have an issue for using ADC5140, pls kindly comments for it, thanks.
- MIC setting as below (Mic 1 ->In 1 ->Out 1-> TDM1)..., we found TDM7 TDM8 o/p phase will have phase shift issue.
2. We modify input source direction, GPI2 to channel 7, 8 ，GPI4 to channel 3, 4,
The result is the same, TDM7 TDM8 has phase shift issue. (modify GPI_CFG0、 GPI_CFG1 registers)
3. Then, modify output direction,
IN3->OUT7->TDM7 , IN4->OUT8->TDM8 (no issue)
IN7->OUT3->TDM3 ，IN8->OUT4->TDM4 (with issue)
Summary,
Except ASI_CHX register, if any others register will possible fix this issue?
Below is the setting for TLV320ADC5140 master and slave.
pdm_reg_setting settings_master[] =
{
{TLV320_REG_PAGE_CFG, 0x00, false},
{TLV320_REG_SW_RESET, 0x01, true},
{TLV320_REG_SLEEP_CFG, 0x81, false},
{TLV320_REG_ASI_CFG0, 0x31, false},
{TLV320_REG_ASI_CFG1, 0xA0, false},
{TLV320_REG_GPIO_CFG0, 0xA0, false},
{TLV320_REG_MST_CFG0, 0x87, false},
{TLV320_REG_MST_CFG1, 0x4A, false},
{TLV320_REG_ASI_CH1, 0x00, false},
{TLV320_REG_ASI_CH2, 0x01, false},
{TLV320_REG_ASI_CH3, 0x02, false},
{TLV320_REG_ASI_CH4, 0x03, false},
{TLV320_REG_ASI_CH5, 0x04, false},
{TLV320_REG_ASI_CH6, 0x05, false},
{TLV320_REG_ASI_CH7, 0x06, false},
{TLV320_REG_ASI_CH8, 0x07, false},
{TLV320_REG_CH1_CFG0, 0x40, false},
{TLV320_REG_CH2_CFG0, 0x40, false},
{TLV320_REG_CH3_CFG0, 0x40, false},
{TLV320_REG_CH4_CFG0, 0x40, false},
{TLV320_REG_GPO_CFG0, 0x41, false},
{TLV320_REG_GPO_CFG1, 0x41, false},
{TLV320_REG_GPO_CFG2, 0x41, false},
{TLV320_REG_GPO_CFG3, 0x41, false},
{TLV320_REG_GPI_CFG0, 0x45, false},
{TLV320_REG_GPI_CFG1, 0x67, false},
{TLV320_REG_IN_CH_EN, 0xFF, false},
{TLV320_REG_ASI_OUT_CH_EN, 0xFF, false},
{0xFF, 0x00, false}
};
pdm_reg_setting settings_slave[] =
{
{TLV320_REG_PAGE_CFG, 0x00, false},
{TLV320_REG_SW_RESET, 0x01, true},
{TLV320_REG_SLEEP_CFG, 0x81, false},
{TLV320_REG_ASI_CFG0, 0x31, false},
{TLV320_REG_ASI_CFG1, 0x80, false},
{TLV320_REG_ASI_CH1, 0x08, false},
{TLV320_REG_ASI_CH2, 0x09, false},
{TLV320_REG_ASI_CH3, 0x0A, false},
{TLV320_REG_ASI_CH4, 0x0B, false},
{TLV320_REG_ASI_CH5, 0x0C, false},
{TLV320_REG_ASI_CH6, 0x0D, false},
{TLV320_REG_ASI_CH7, 0x0E, false},
{TLV320_REG_ASI_CH8, 0x0F, false},
{TLV320_REG_CH1_CFG0, 0x40, false},
{TLV320_REG_CH2_CFG0, 0x40, false},
{TLV320_REG_CH3_CFG0, 0x40, false},
{TLV320_REG_CH4_CFG0, 0x40, false},
{TLV320_REG_GPO_CFG0, 0x41, false},
{TLV320_REG_GPO_CFG1, 0x41, false},
{TLV320_REG_GPO_CFG2, 0x41, false},
{TLV320_REG_GPO_CFG3, 0x41, false},
{TLV320_REG_GPI_CFG0, 0x45, false},
{TLV320_REG_GPI_CFG1, 0x67, false},
{TLV320_REG_IN_CH_EN, 0xFF, false},
{TLV320_REG_ASI_OUT_CH_EN, 0xFF, false},
{0xFF, 0x00, false}
};
Thanks, Ian.
