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PCM1840: Clock timing requirement in Slave mode

Mochi
Genius 3865 points
Part Number: PCM1840

Hello,

Our customer plans to use PCM1840 in slave mode.

To review their inputted BCK clock timing from DSP, which specification should we referred?

Section 6.6 Timing Requirements noted “all outputs”, we expect this specification is in Master mode PCM1840 will output PCM data as following timing specification. Is that correct?

   6.6 Timing Requirements: TDM, I2S or LJ Interface

   at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram

 

One more curiosity is definition of rise and fall time on the datasheet, for output node 10-90% is reasonable.

However for input node as Slave mode BCK pin input, clock timing might be defined by Vth H(max) and Vth L(min), it is not 10%-90%. Can we read the specification with this definition in Slave mode?

   tr(BCLK) BCLK rise time  10% - 90% rise time  10 ns

   tf(BCLK) BCLK fall time    90% - 10% fall time    10 ns

Because, mass production products have dumping resistors for those clock lines. Rise and fall time became longer to get better EMI characteristics.

Regards,

Mochizuki

  • 0
    TI__Mastermind 23050 points

    Hi Mochizuki,

    Rise and fall times are typically defined as 10%-90% regardless of the threshold for high and low, but this is included in the conditions for rise and fall time specs as well. Ideally the dumping resistors should be sized to maintain rise and fall times below the maximum specified in the datasheet.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 3865 points

    Hello Zak,

    I appreciate your prompt reply.

     

    Okay, I can see same clock timing definition on TLV320ADC3104, it looks historically your design team use this timing requirement.

    Could you clarify one thing, Is this 6.6 section specification cover both of Master and Slave mode?

     

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 23050 points

    Hey Mochizuki,

    Table 6.6 is input timing requirements and generally applies to the device operating in slave mode. Table 6.7 is switching characteristics and lists the behavior of the pins as outputs in master mode as well as the timing of the SDOUT pin, which is always an output.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 3865 points

    Hi Zak,

    Our customer is facing difficulty to maintain 10nsec rising/falling time requirement because even they remove dumping resistor DSP cannot drive so rapidly. They need to add clock buffer to meet this requirements.

    However they used be using competitor A’s ADC, their timing requirement is followings.

    It is specified minimum BCK pulse Width timing only, based on Vth voltage clock timing there is no 10-90% slew rate requirements also value is varied based on fs setting, BCK rate.

     

    From engineer’s view point it is very easy to understand the reason why this requirement is needed from ADC device function.

    In the case of PCM1840 and TLV320ADCxxxx, it is required absolute fix value 10nsec 10-90% no consideration fs setting and effective pulse width based on Vth point. So our customer is now frustrated this difference.

    They want to know what happen if rising and falling time is reach to 15nsec at fs=48KHz 64BCK=3.072MHz=325.5nsec condition? It may not same as TDM 384BCK=18.432MHz=15nsec environment.

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

    I know it is matter of system/design specification, at this moment we cannot do anything. But do your team have any good idea to relax and exception requirement at Low BCK clock rate at non TDM format environment in audio ADC market.

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     


     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

    Hi Zak,

    Our customer is facing difficulty to maintain 10nsec rising/falling time requirement because even they remove dumping resistor DSP cannot drive so rapidly. They need to add clock buffer to meet this requirements.

    However they used be using competitor A’s ADC, their timing requirement is followings.

    It is specified minimum BCK pulse Width only, based on Vth voltage clock timing, there is no 10-90% slew rate requirement also value is varied based on fs setting, BCK rate.

    From engineer’s view point it is very easy to understand the reason why this requirement is needed from ADC device function.

    In the case of PCM1840 and TLV320ADCxxxx, it is required absolute fix value 10nsec 10-90% no consideration fs setting and effective pulse width based on Vth point. So our customer is now frustrated this difference.

    They want to know what happen if rising and falling time is reach to 15nsec at fs=48KHz 64BCK=3.072MHz=325.5nsec condition? It may not same as TDM 384BCK=18.432MHz=15nsec environment.

    I know it is matter of system/design specification, at this moment we cannot do anything. But do your team have any good idea to relax and exception requirement at Low BCK clock rate at non TDM format environment in this audio ADC market.

    Regards,

    Mochziuki

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  • 0 in reply to Mochi
    Genius 3865 points

    Hello,

    My previous post was something duplicate the documents.

    Please scroll it to bottom line.

     

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 23050 points

    Hi Mochi,

    It is true that the 10nsec value is a worst case spec and the device is a bit more tolerable to the rise and fall times being slightly longer at slower clock speeds, but we don't specify this at different BCLK values. The clock edge needs to be fast so to limit the jitter introduced to the PLL to maintain high THD+N performance. In general I would say 12ns is acceptable at the slower clock speeds you have described, but again we do not specify this as such and I can't say what amount of degradation might occur at 15ns. I think it is best to include a buffer if they are having trouble meeting the spec.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 3865 points

    Hi Zak,

    I appreciate your kindly support, we got the customers understandings.

    Regards,

    Mochizuki