Hi team,
Our customer drew a schematic diagram of a power amplifier(TAS6424-Q1), see the attachment, using 19 TAS6424-Q1s, the signal is provided by FPGA;
Among them, I2S signal and I2C signal need to share GPIO, MCLK, SCLK and FSYNC are shared by four TAS6424-Q1s; I2C bus is also shared by four TAS6424-Q1s, and the I2C_ADDR0 and I2C_ADDR1 of the four ICs are set to different addresses.
And, Can I put down the MUTE signal and STANDBY signal?
In addition, please check for other errors
I will send the file from e-mail.
