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TAS6424-Q1: About the power supply sequence on the boost power mode

user6388211
Prodigy 220 points
Part Number: TAS6424-Q1

Hello team

I  want to high power output 50W@THD3%;4ohm by TAS6424-Q1.

In this case, the supply voltage to PVDD is 22V. But, if 22V input to VBAT, TAS6424-Q1 is shutdown by the OverVoltage (OV).

**The Battery voltage is 24V system. 22V is made by Buck-Boost  converter.

I'm thinking of making 12V from 22V, but the description below is in Section [10.3.9.2 Boosted Power-Supply Sequence ], 

『In this case, the VBAT and PVDD inputs are not connected to the same supply.
When powering up, apply the VBAT supply first, the VDD supply second, and the PVDD supply last.
When powering down, remove the PVDD supply first, the VDD supply second, and the VBAT supply last.』

~Question~

What are the concerns when inputting in the order of PVDD -> VBAT -> VDD? What happens at the IC?

I am thinking of using PVDD -> VBAT -> VDD in the power-on sequence and VDD -> VBAT -> PVDD in the power-down sequence.

  • 0
    TI__Mastermind 34265 points

    Hello,

    This will depend on your method to derive the 12Vdc from the 22Vdc voltage.  If they both turn on at the same time, the VBAT will reach 12Vdc before the 22Vdc.  Then you sequencing is correct.  If you turn on the VBAT voltage after the PVDD voltage then you will have an incorrect sequence.  The problem with the PVDD being on before the VBAT is that the gate drive is not stable before the PVDD is powered on. It is highly recommended that the datasheet sequence is used to guarantee that the device will behave on turn-on every time.

  • +1 in reply to Gregg Scott
    Prodigy 220 points

    I don't understand your answer [The problem with the PVDD being on before the VBAT is that the gate drive is not stable before the PVDD is powered on. ]

    If the gate driver needs to be stable before supplying PVDD, I think that VBAT and PVDD cannot be supplied at the same time

    even if it is not used for boosting.

    And, I think this is not issue because standby pin is set to low during the voltage supply timing.

    The voltage supply to Drain of N-ch FET at first, it is same using at DCDC converter, right?

    My understanding is that the gate drive is need to stable before standby pin set to high.

    So, is it necessary to care about the supply order of PVDD and VBAT before canceling standby?

    Please let me know if my understanding is wrong.

  • 0 in reply to user6388211
    TI__Mastermind 34265 points

    As power supplies rise, there can be unknown states until they are stable, even if he standby pin is low.  This is all I was trying to say.  When VBAT and PVDD rise together, it will behave.  When not tied together, there is a possibility of an unknown state.  We recommend to use the datasheet sequence.  As I stated, if VBAT is derived from the PVDD boost, it should rise at the same time and should meet our datasheet recommendation.