TLV320AIC3104: TLV320AIC3104 issue

Cooper Zhang1

Part Number: TLV320AIC3104

Dear ，

customer use it ,they meet two issue, please kindly help me give any suggestion

1. condition ：using PC to record，then to play with earphone; Question ：when the chip has not been initialized yet, at this moment, it found that there is crosstalk, the earphone can hear a little bit of the recorded sound; But using notebook to record, there is no such problem as above ;

2.in master mode , record and play are all ok, however, in slave mode, there will be noise, customer tried to change Fs frequency， but no effect; we doubt 32bit missed the highest bit, try to left alignment and delay WL and SCLK , we can not solve the problem, so I need your help to give me any suggestion;

note: currently customer use schematic as below

over 3 years ago

0 Aaron Estrada over 3 years ago

TI__Mastermind 22950 points

Hi Cooper,

Can you please provide a full I2C register dump? It may be that this could be a configuration problem. If you are testing in both master and slave mode, please send the register dump for both configurations. In slave mode, it would also be helpful if you can provide the clock information such as MCLK, BCLK and WCLK frequencies.

Regarding the 1st condition, you say that crosstalk exists when the device has not been initialized. What is the state of the device prior to initialization?

Regards,

Aaron Estrada

0 Cooper Zhang1 over 3 years ago in reply to Aaron Estrada

Expert 2190 points

Dear Aaron:

Both the master and slave mode register as attached， please find it； In slave mode ，MCLK 37.13M，BCLK 3.072M，WCLK 48K

however, Regarding the 1st condition， you can understand crosstalk exists when the power is ok , at this moment the chip is not soft reset;

reg_dump_in_master_rx.txt

Tlv320 Master Rx，mclk约为37.125MHz。

tlv320 reg[0] = 0x0
tlv320 reg[1] = 0x0
tlv320 reg[2] = 0x0
tlv320 reg[3] = 0x92
tlv320 reg[4] = 0x14
tlv320 reg[5] = 0x2e
tlv320 reg[6] = 0x38
tlv320 reg[7] = 0xa
tlv320 reg[8] = 0xc0
tlv320 reg[9] = 0x30
tlv320 reg[10] = 0x0
tlv320 reg[11] = 0x1
tlv320 reg[12] = 0x0
tlv320 reg[13] = 0x0
tlv320 reg[14] = 0x0
tlv320 reg[15] = 0x0
tlv320 reg[16] = 0x0
tlv320 reg[17] = 0xf
tlv320 reg[18] = 0xf0
tlv320 reg[19] = 0x7c
tlv320 reg[20] = 0x78
tlv320 reg[21] = 0x78
tlv320 reg[22] = 0x7c
tlv320 reg[23] = 0x78
tlv320 reg[24] = 0x78
tlv320 reg[25] = 0x6
tlv320 reg[26] = 0x0
tlv320 reg[27] = 0xfe
tlv320 reg[28] = 0x0
tlv320 reg[29] = 0x0
tlv320 reg[30] = 0xfe
tlv320 reg[31] = 0x0
tlv320 reg[32] = 0x0
tlv320 reg[33] = 0x0
tlv320 reg[34] = 0x0
tlv320 reg[35] = 0x0
tlv320 reg[36] = 0x44
tlv320 reg[37] = 0x0
tlv320 reg[38] = 0x0
tlv320 reg[39] = 0x0
tlv320 reg[40] = 0x0
tlv320 reg[41] = 0x0
tlv320 reg[42] = 0x0
tlv320 reg[43] = 0x80
tlv320 reg[44] = 0x80
tlv320 reg[45] = 0x0
tlv320 reg[46] = 0x0
tlv320 reg[47] = 0x0
tlv320 reg[48] = 0x0
tlv320 reg[49] = 0x0
tlv320 reg[50] = 0x0
tlv320 reg[51] = 0x4
tlv320 reg[52] = 0x0
tlv320 reg[53] = 0x0
tlv320 reg[54] = 0x0
tlv320 reg[55] = 0x0
tlv320 reg[56] = 0x0
tlv320 reg[57] = 0x0
tlv320 reg[58] = 0x4
tlv320 reg[59] = 0x0
tlv320 reg[60] = 0x0
tlv320 reg[61] = 0x0
tlv320 reg[62] = 0x0
tlv320 reg[63] = 0x0
tlv320 reg[64] = 0x0
tlv320 reg[65] = 0x4
tlv320 reg[66] = 0x0
tlv320 reg[67] = 0x0
tlv320 reg[68] = 0x0
tlv320 reg[69] = 0x0
tlv320 reg[70] = 0x0
tlv320 reg[71] = 0x0
tlv320 reg[72] = 0x4
tlv320 reg[73] = 0x0
tlv320 reg[74] = 0x0
tlv320 reg[75] = 0x0
tlv320 reg[76] = 0x0
tlv320 reg[77] = 0x0
tlv320 reg[78] = 0x0
tlv320 reg[79] = 0x0
tlv320 reg[80] = 0x0
tlv320 reg[81] = 0x0
tlv320 reg[82] = 0x0
tlv320 reg[83] = 0x0
tlv320 reg[84] = 0x0
tlv320 reg[85] = 0x0
tlv320 reg[86] = 0x0
tlv320 reg[87] = 0x0
tlv320 reg[88] = 0x0
tlv320 reg[89] = 0x0
tlv320 reg[90] = 0x0
tlv320 reg[91] = 0x0
tlv320 reg[92] = 0x0
tlv320 reg[93] = 0x0
tlv320 reg[94] = 0x0
tlv320 reg[95] = 0x0
tlv320 reg[96] = 0x0
tlv320 reg[97] = 0x0
tlv320 reg[98] = 0x0
tlv320 reg[99] = 0x0
tlv320 reg[100] = 0x0
tlv320 reg[101] = 0x0
tlv320 reg[102] = 0x2
tlv320 reg[103] = 0x0
tlv320 reg[104] = 0x0
tlv320 reg[105] = 0x0
tlv320 reg[106] = 0x0
tlv320 reg[107] = 0x0
tlv320 reg[108] = 0x0
tlv320 reg[109] = 0x0

reg_dump_in_master_tx.txt

Tlv320 Master Tx，mclk约为37.125MHz。

tlv320 reg[0] = 0x0
tlv320 reg[1] = 0x0
tlv320 reg[2] = 0x0
tlv320 reg[3] = 0x92
tlv320 reg[4] = 0x14
tlv320 reg[5] = 0x2e
tlv320 reg[6] = 0x38
tlv320 reg[7] = 0xa
tlv320 reg[8] = 0xc0
tlv320 reg[9] = 0x30
tlv320 reg[10] = 0x0
tlv320 reg[11] = 0x1
tlv320 reg[12] = 0x0
tlv320 reg[13] = 0x0
tlv320 reg[14] = 0x0
tlv320 reg[15] = 0xa0
tlv320 reg[16] = 0xa0
tlv320 reg[17] = 0xff
tlv320 reg[18] = 0xff
tlv320 reg[19] = 0x78
tlv320 reg[20] = 0x78
tlv320 reg[21] = 0x78
tlv320 reg[22] = 0x78
tlv320 reg[23] = 0x78
tlv320 reg[24] = 0x78
tlv320 reg[25] = 0x6
tlv320 reg[26] = 0x0
tlv320 reg[27] = 0xfe
tlv320 reg[28] = 0x0
tlv320 reg[29] = 0x0
tlv320 reg[30] = 0xfe
tlv320 reg[31] = 0x0
tlv320 reg[32] = 0x0
tlv320 reg[33] = 0x0
tlv320 reg[34] = 0x0
tlv320 reg[35] = 0x0
tlv320 reg[36] = 0x0
tlv320 reg[37] = 0xc0
tlv320 reg[38] = 0x0
tlv320 reg[39] = 0x0
tlv320 reg[40] = 0x0
tlv320 reg[41] = 0x0
tlv320 reg[42] = 0x0
tlv320 reg[43] = 0x0
tlv320 reg[44] = 0x0
tlv320 reg[45] = 0x0
tlv320 reg[46] = 0x0
tlv320 reg[47] = 0xaf
tlv320 reg[48] = 0x0
tlv320 reg[49] = 0x0
tlv320 reg[50] = 0x0
tlv320 reg[51] = 0xf
tlv320 reg[52] = 0x0
tlv320 reg[53] = 0x0
tlv320 reg[54] = 0x0
tlv320 reg[55] = 0x0
tlv320 reg[56] = 0x0
tlv320 reg[57] = 0x0
tlv320 reg[58] = 0x6
tlv320 reg[59] = 0x0
tlv320 reg[60] = 0x0
tlv320 reg[61] = 0x0
tlv320 reg[62] = 0x0
tlv320 reg[63] = 0x0
tlv320 reg[64] = 0xaf
tlv320 reg[65] = 0xf
tlv320 reg[66] = 0x0
tlv320 reg[67] = 0x0
tlv320 reg[68] = 0x0
tlv320 reg[69] = 0x0
tlv320 reg[70] = 0x0
tlv320 reg[71] = 0x0
tlv320 reg[72] = 0x6
tlv320 reg[73] = 0x0
tlv320 reg[74] = 0x0
tlv320 reg[75] = 0x0
tlv320 reg[76] = 0x0
tlv320 reg[77] = 0x0
tlv320 reg[78] = 0x0
tlv320 reg[79] = 0x0
tlv320 reg[80] = 0x0
tlv320 reg[81] = 0x0
tlv320 reg[82] = 0x0
tlv320 reg[83] = 0x0
tlv320 reg[84] = 0x0
tlv320 reg[85] = 0x0
tlv320 reg[86] = 0x0
tlv320 reg[87] = 0x0
tlv320 reg[88] = 0x0
tlv320 reg[89] = 0x0
tlv320 reg[90] = 0x0
tlv320 reg[91] = 0x0
tlv320 reg[92] = 0x0
tlv320 reg[93] = 0x0
tlv320 reg[94] = 0xc6
tlv320 reg[95] = 0xc
tlv320 reg[96] = 0x0
tlv320 reg[97] = 0x0
tlv320 reg[98] = 0x0
tlv320 reg[99] = 0x0
tlv320 reg[100] = 0x0
tlv320 reg[101] = 0x0
tlv320 reg[102] = 0x2
tlv320 reg[103] = 0x0
tlv320 reg[104] = 0x0
tlv320 reg[105] = 0x0
tlv320 reg[106] = 0x0
tlv320 reg[107] = 0x0
tlv320 reg[108] = 0x0
tlv320 reg[109] = 0x0

reg_dump_in_slave_rx.txt

Tlv320 Slave Rx，mclk约为12.288MHz。

tlv320 reg[0] = 0x0
tlv320 reg[1] = 0x0
tlv320 reg[2] = 0x0
tlv320 reg[3] = 0x10
tlv320 reg[4] = 0x4
tlv320 reg[5] = 0x0
tlv320 reg[6] = 0x0
tlv320 reg[7] = 0xa
tlv320 reg[8] = 0x0
tlv320 reg[9] = 0x30
tlv320 reg[10] = 0x0
tlv320 reg[11] = 0x1
tlv320 reg[12] = 0x0
tlv320 reg[13] = 0x0
tlv320 reg[14] = 0x0
tlv320 reg[15] = 0x0
tlv320 reg[16] = 0x0
tlv320 reg[17] = 0xf
tlv320 reg[18] = 0xf0
tlv320 reg[19] = 0x7c
tlv320 reg[20] = 0x78
tlv320 reg[21] = 0x78
tlv320 reg[22] = 0x7c
tlv320 reg[23] = 0x78
tlv320 reg[24] = 0x78
tlv320 reg[25] = 0x6
tlv320 reg[26] = 0x0
tlv320 reg[27] = 0xfe
tlv320 reg[28] = 0x0
tlv320 reg[29] = 0x0
tlv320 reg[30] = 0xfe
tlv320 reg[31] = 0x0
tlv320 reg[32] = 0x0
tlv320 reg[33] = 0x0
tlv320 reg[34] = 0x0
tlv320 reg[35] = 0x0
tlv320 reg[36] = 0x44
tlv320 reg[37] = 0x0
tlv320 reg[38] = 0x0
tlv320 reg[39] = 0x0
tlv320 reg[40] = 0x0
tlv320 reg[41] = 0x0
tlv320 reg[42] = 0x0
tlv320 reg[43] = 0x80
tlv320 reg[44] = 0x80
tlv320 reg[45] = 0x0
tlv320 reg[46] = 0x0
tlv320 reg[47] = 0x0
tlv320 reg[48] = 0x0
tlv320 reg[49] = 0x0
tlv320 reg[50] = 0x0
tlv320 reg[51] = 0x4
tlv320 reg[52] = 0x0
tlv320 reg[53] = 0x0
tlv320 reg[54] = 0x0
tlv320 reg[55] = 0x0
tlv320 reg[56] = 0x0
tlv320 reg[57] = 0x0
tlv320 reg[58] = 0x4
tlv320 reg[59] = 0x0
tlv320 reg[60] = 0x0
tlv320 reg[61] = 0x0
tlv320 reg[62] = 0x0
tlv320 reg[63] = 0x0
tlv320 reg[64] = 0x0
tlv320 reg[65] = 0x4
tlv320 reg[66] = 0x0
tlv320 reg[67] = 0x0
tlv320 reg[68] = 0x0
tlv320 reg[69] = 0x0
tlv320 reg[70] = 0x0
tlv320 reg[71] = 0x0
tlv320 reg[72] = 0x4
tlv320 reg[73] = 0x0
tlv320 reg[74] = 0x0
tlv320 reg[75] = 0x0
tlv320 reg[76] = 0x0
tlv320 reg[77] = 0x0
tlv320 reg[78] = 0x0
tlv320 reg[79] = 0x0
tlv320 reg[80] = 0x0
tlv320 reg[81] = 0x0
tlv320 reg[82] = 0x0
tlv320 reg[83] = 0x0
tlv320 reg[84] = 0x0
tlv320 reg[85] = 0x0
tlv320 reg[86] = 0x0
tlv320 reg[87] = 0x0
tlv320 reg[88] = 0x0
tlv320 reg[89] = 0x0
tlv320 reg[90] = 0x0
tlv320 reg[91] = 0x0
tlv320 reg[92] = 0x0
tlv320 reg[93] = 0x0
tlv320 reg[94] = 0x0
tlv320 reg[95] = 0x0
tlv320 reg[96] = 0x0
tlv320 reg[97] = 0x0
tlv320 reg[98] = 0x0
tlv320 reg[99] = 0x0
tlv320 reg[100] = 0x0
tlv320 reg[101] = 0x1
tlv320 reg[102] = 0x2
tlv320 reg[103] = 0x0
tlv320 reg[104] = 0x0
tlv320 reg[105] = 0x0
tlv320 reg[106] = 0x0
tlv320 reg[107] = 0x0
tlv320 reg[108] = 0x0
tlv320 reg[109] = 0x0

reg_dump_in_slave_tx.txt

Tlv320 Slave Tx，mclk约为12.288MHz。

tlv320 reg[0] = 0x0
tlv320 reg[1] = 0x0
tlv320 reg[2] = 0x0
tlv320 reg[3] = 0x10
tlv320 reg[4] = 0x4
tlv320 reg[5] = 0x0
tlv320 reg[6] = 0x0
tlv320 reg[7] = 0xa
tlv320 reg[8] = 0x0
tlv320 reg[9] = 0x30
tlv320 reg[10] = 0x0
tlv320 reg[11] = 0x1
tlv320 reg[12] = 0x0
tlv320 reg[13] = 0x0
tlv320 reg[14] = 0x0
tlv320 reg[15] = 0xa0
tlv320 reg[16] = 0xa0
tlv320 reg[17] = 0xff
tlv320 reg[18] = 0xff
tlv320 reg[19] = 0x78
tlv320 reg[20] = 0x78
tlv320 reg[21] = 0x78
tlv320 reg[22] = 0x78
tlv320 reg[23] = 0x78
tlv320 reg[24] = 0x78
tlv320 reg[25] = 0x6
tlv320 reg[26] = 0x0
tlv320 reg[27] = 0xfe
tlv320 reg[28] = 0x0
tlv320 reg[29] = 0x0
tlv320 reg[30] = 0xfe
tlv320 reg[31] = 0x0
tlv320 reg[32] = 0x0
tlv320 reg[33] = 0x0
tlv320 reg[34] = 0x0
tlv320 reg[35] = 0x0
tlv320 reg[36] = 0x0
tlv320 reg[37] = 0xc0
tlv320 reg[38] = 0x0
tlv320 reg[39] = 0x0
tlv320 reg[40] = 0x0
tlv320 reg[41] = 0x0
tlv320 reg[42] = 0x0
tlv320 reg[43] = 0x0
tlv320 reg[44] = 0x0
tlv320 reg[45] = 0x0
tlv320 reg[46] = 0x0
tlv320 reg[47] = 0xaf
tlv320 reg[48] = 0x0
tlv320 reg[49] = 0x0
tlv320 reg[50] = 0x0
tlv320 reg[51] = 0xf
tlv320 reg[52] = 0x0
tlv320 reg[53] = 0x0
tlv320 reg[54] = 0x0
tlv320 reg[55] = 0x0
tlv320 reg[56] = 0x0
tlv320 reg[57] = 0x0
tlv320 reg[58] = 0x6
tlv320 reg[59] = 0x0
tlv320 reg[60] = 0x0
tlv320 reg[61] = 0x0
tlv320 reg[62] = 0x0
tlv320 reg[63] = 0x0
tlv320 reg[64] = 0xaf
tlv320 reg[65] = 0xf
tlv320 reg[66] = 0x0
tlv320 reg[67] = 0x0
tlv320 reg[68] = 0x0
tlv320 reg[69] = 0x0
tlv320 reg[70] = 0x0
tlv320 reg[71] = 0x0
tlv320 reg[72] = 0x6
tlv320 reg[73] = 0x0
tlv320 reg[74] = 0x0
tlv320 reg[75] = 0x0
tlv320 reg[76] = 0x0
tlv320 reg[77] = 0x0
tlv320 reg[78] = 0x0
tlv320 reg[79] = 0x0
tlv320 reg[80] = 0x0
tlv320 reg[81] = 0x0
tlv320 reg[82] = 0x0
tlv320 reg[83] = 0x0
tlv320 reg[84] = 0x0
tlv320 reg[85] = 0x0
tlv320 reg[86] = 0x0
tlv320 reg[87] = 0x0
tlv320 reg[88] = 0x0
tlv320 reg[89] = 0x0
tlv320 reg[90] = 0x0
tlv320 reg[91] = 0x0
tlv320 reg[92] = 0x0
tlv320 reg[93] = 0x0
tlv320 reg[94] = 0xc6
tlv320 reg[95] = 0xc
tlv320 reg[96] = 0x0
tlv320 reg[97] = 0x0
tlv320 reg[98] = 0x0
tlv320 reg[99] = 0x0
tlv320 reg[100] = 0x0
tlv320 reg[101] = 0x1
tlv320 reg[102] = 0x2
tlv320 reg[103] = 0x0
tlv320 reg[104] = 0x0
tlv320 reg[105] = 0x0
tlv320 reg[106] = 0x0
tlv320 reg[107] = 0x0
tlv320 reg[108] = 0x0
tlv320 reg[109] = 0x0

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TLV320AIC3104: TLV320AIC3104 issue