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TLV320ADC3101: Question of TLV320ADC3101 Register 0x3d and 0x15 With MiniDSP

Part Number: TLV320ADC3101

Hi Sirs,

As a following of the thread of e2e.ti.com/.../tlv320adc3101-question-of-purepath-studio-gde-for-tlv320adc3101-minidsp-for-4ch-tdm-recording

Customer got no sound issue with the programming sequence of:

(1) Write Page 0x00~Page 0x04,
(2) Write Page 0x20~0x2F.
(3) Write Page 0x00 Register 0x3d=0x00 (Enable MiniDSP)

According to I2C dump data, the 0x3d hen been written to 0x00 correctly.



According to the datasheet, when we write 0x3d=0x00, we should update register 0x15 accordingly. However, customer keeps getting no sound issue when trying to write 0x15 = 0xff. Would you pls advise how to program the 0x15 properly?

     
Thank you and Best regards,

Wayne Chen
04/29/2021


  • Hey Wayne,

    There are a few restrictions on how the MiniDSP must be configured. They are:

    1) MCLK must be >IADC*Fs, or in this case 510*44.1kHz = 22.491MHz. The typical multiple would be 22.5792MHz here so please be sure the clock is configured as such

    2) MADC x AOSR >= IADC

    3) The AOSR and IADC must both be integer multiple of the decimation factor

    It looks like the AOSR is set to 128 from your register dump, so when IADC = 510 condition 2 is no longer satisfied. You need to increase the AOSR or adjust the MADC divider for the audio to work.

    Best,

    Zak

  • Hello Zak,

    Thank you for your elaborate. We will check customer's clock configurations. This is why we also suggested product line to combine the PurePath Studio and Codec Control GUI together to generate a valid CFG for customer's system integration.

    Addition, can we say that we are not able to enable the MiniDSP with customer's existing clock configurations. Is it a limitation of the TLV320ADC3101's MiniDSP?  

    Thank you and Best regards,

    Wayne Chen
    05/04/2021 

  • Hey Wayne,

    My apologies, I missed your follow up question. The problem is that you are setting the miniDSP to run with an instruction count for which there are not enough clock cycles to support. I wouldn't really say this is a limitation of the miniDSP, so much as it is just an invalid configuration.

    Best,

    Zak

  • Thank you for your advise, Zak...Wayne Chen