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PCM1864-Q1: Gain problems

Georgii Zagoruiko
Prodigy 190 points

Part Number: PCM1864-Q1
Other Parts Discussed in Thread: PCM1864

Hello everyone!
We have a problem with the input signal, we have the following connection scheme: the microphone is connected to CH1 L, the speaker signal with a divider is connected to CH2 L. The problem is the following: the amplification of the signal from the microphone is adjusted correctly for any channel (CH1 L / CH2 L), and the signal level from the speaker at any value of digital or analog gain remains minimal, barely audible. Once or twice, I observed a picture that the signal was very strong at maximum digital gain, but now this again does not work. Tell me if you have any thoughts on this?

Bes regards,
Georgy Zagoruiko

  • 0
    TI__Guru**** 182521 points

    Hi Georgy,

    Can you provide the register details from the PCM1864-Q1and perhaps a schematic of the area around the ADC?

  • 0 in reply to Tom Hendrick
    Prodigy 190 points

    Hi, Tom! Thank you for reply!

    I didn't see your answer...

    PCM1864 settings work correct for MIC without speaker signal connection. I'll send you schematic later

  • 0 in reply to Tom Hendrick
    Prodigy 190 points 

    {0x00, 0xFE}, /* Reset the registers */
{0x00, 0x00}, /* Set register page to 0x00 */
{0x60, 0x0},  /* Turn off energy sense */
/* Clock settings for 16KHz */
{0x20, 0x32}, /* SCK_XI_SEL=SCK|Xtal, MST_SCK_SRC=PLL, MST_MODE=Master, ADC_CLK_SRC=SCK,
                 DSP2_CLK_SRC=SCK, DSP1_CLK_SRC=PLL, CLKDET_EN=Disable */
{0x21, 0x0B}, /* PLL to DSP1 Divide value = 1/12 */
{0x22, 0x03}, /* SCK to DSP2 Divide value = 1/4 */
{0x23, 0x0B}, /* SCK to ADC Divide value = 1/12 */
{0x25, 0x07}, /* PLL to SCK OUT divider = 1/8 */
{0x26, 0x0B}, /* SCK to BCK divider = 1/12 */
{0x27, 0x3F}, /* BCK to LRCK divider = 1/64 */
{0x29, 0x07}, /* P Divide value = 1/8 */
{0x2A, 0x01}, /* R Multiplier value = 2 */
{0x2B, 0x10}, /* J Multiplier value = 16 (Integer part of K=J.D) */
{0x28, 0x01}, /* PLL_REF_SEL=SCK; PLL_EN=Enabled */
{0xFF, 0x0},  /* wait for PLL to lock */
{0x19, 0xFF}, /* Manual gain mapping */
{0x01, 0x0},  /* PGA CH1_L */
{0x02, 0x0},  /* PGA CH1_R */
{0x03, 0x0},  /* PGA CH2_L */
{0x04, 0x0},  /* PGA CH2_R */
{0x0F, 0x36}, /* Digital PGA CH1_L (7dB) */
{0x17, 0x28}, /* Digital PGA CH2_L (0dB) */
{0x06, 0x41}, /* Polarity: Normal, Channel: VINL1[SE] */
{0x07, 0x44}, /* Polarity: Normal, Channel: VINR3[SE] */
{0x08, 0x42}, /* Polarity: Normal, Channel: VINL2[SE] */
{0x09, 0x48}, /* Polarity: Normal, Channel: VINR4[SE] */
{0x0B, 0x0C}, /* TX WLEN: 16 bit; FMT: I2S format */
{0x10, 0x03}, /* GPIO0_FUNC - SCK Out; GPIO0_POL - Normal */
{0x11, 0x50}, /* GPIO3_FUNC - DOUT2; GPIO3_POL - Normal */
{0x12, 0x04}, /* GPIO0_DIR - GPIO0 - Output */
{0x13, 0x40}  /* GPIO3_DIR – GPIO3 - Output */

  • 0 in reply to Tom Hendrick
    Prodigy 190 points

    Speaker signal to ADC schema

  • 0 in reply to Georgii Zagoruiko
    TI__Mastermind 23050 points

    Hi Georgii,

    One thing to consider is that the PCM186x has a single-ended input impedance of 10kOhms, and this is going to heavily influence the resistor divider shown. Effectively your divider ratio goes from 0.133 to .025, which means the signal is nearly 5.5 times smaller due to the loading from the ADC. You would either want to use much smaller resistor values (probably not desirable from a power consumption standpoint) or buffer the speaker signal prior to the ADC.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 190 points

    Hi, Zak!

    Thank you for you answer!

    I understand why the signal can be very small, but why my gain can jump?
    In one case, if the signal from the speaker has a normal (expected) gain, then the microphone signal is too high (although it is set to a normal gain, for example -15dBFS).
    Otherwise, if the microphone signal has the expected gain (-15dBFS), then the signal from the speaker is extremely small.
    If you catch the right time, then both signals sometimes have the correct amplification.

    Best regards,

    Georgii Zagoruiko

  • 0 in reply to Georgii Zagoruiko
    TI__Mastermind 23050 points

    Hi Georgii,

    I think there may be an issue with your DSP2 clock. Can you try setting the SCK to DSP2 divider to 6 instead of 4? Also, this device does have an autoclock configuration feature so you don't need to manually configure the dividers. Is there a reason you prefer not to use this feature?

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 190 points

    Hi Zak,

    Thank you for your quick answer!

    I set up the ADC in such a way as to better understand the settings. You can try to return the settings to the original ones. Why do you think there might be a problem with DSP2? My curiosity :)

    In the absence of a connected signal from the speaker, everything works stably...

    I'll try setting the SCK to DSP2 divider to 6 instead of 4, but it will take time.

    Best regards,

    Georgii Zagoruiko

  • 0 in reply to Georgii Zagoruiko
    TI__Mastermind 23050 points

    Hey Georgii,

    I'm using the PLL calculator tool for reference and the DSP2 clock is supposed to be half of the DSP1 clock. Here are the ideal settings.

    Best,

    Zak