Audio forum - Recent Threads

PUREPATH-CMBEVM: PurePathConsole Access DENIED

Ronald Lijs — Thu, 22 Oct 2026 06:35:18 GMT

Part Number: PUREPATH-CMBEVM

Please, can you help me? I've got alerady a customPCB with 2x TAS5825 and x TAS5830 for a project and need urgent access to PurePathConsole 3.

When I requested access, it took 3 days and it was denied :-(

How can I get hld of this software as need urgently to get my multichannel Audio Amp working asap?

We are a real small company based out of France and it's hard to believe we are denied access to such an essential tool from TI.

Thanks in advance for your time!

Ronald
Flash Arcade SARL
FRANCE

RE: PUREPATH-CMBEVM: PurePathConsole Access DENIED

Shenghao Ding — Sun, 01 Nov 2026 00:00:49 GMT

Our expert will feedback you next working day.

RE: TLV320AIC3104: Output channel "FLC" issue

Falguni Sharma — Sat, 31 Oct 2026 09:50:39 GMT

Hello,
I m already doing the same for the registers section as you suggested but still the problem is there.

We are trying to obtain an output from HPL_COM, which has a DC voltage of 1.35 V. The signal passes through an RC low-pass filter and a 47 µF(C3) capacitor, which blocks the DC component and allows the AC signal to pass.

At the FLP and FRP outputs, the voltage remains at ground level. However, at FLC and FRC , the voltage drifts to 1.35 V. When we connect a 100 kΩ resistor between FLC and GND, the voltage returns to ground level.

What would be the best resistor value to keep FLC at ground level without introducing significant distortion or other issues?

TLV320AIC3104: Output channel "FLC" issue

Falguni Sharma — Tue, 27 Oct 2026 10:30:07 GMT

Part Number: TLV320AIC3104

We are currently using the TLV320AIC3104 for our application.

We want three independent volume controllable outputs, so we want to use FLC as an independent output.

The problem we are currently facing is that when I connect FLC to the onboard RC filter, it does not stay at the ground reference and instead drifts to a 1.3 V offset. However, when I connect a 100 kOhm resistor from FLC to ground, it stays at the ground reference.

What we want to know is the best resistor value or solution to keep FLC at the ground reference without any stability or offset drift issues.

Regards,
Falguni Sharma

RE: PUREPATH-CMBEVM: PurePathConsole Access DENIED

Ronald Lijs — Sat, 31 Oct 2026 08:08:25 GMT

Hi there, please could you be so kind as to escalate the PPC3 access request through TI support so they can to escalate via the marketing team for approval of this request? The email address used initially (and the one I' using as part of TI Web access) is: info@casharcade.fr)

Casharcade.fr is a corporate domain own by our company here in France.

The Part Numbers needed are:

PPC3 base application

TAS5825-SW device app

TAS5830-SW device app

We have already an ongoing working project with 2x TAS5825 and x 1x TAS5830 on the same board for active DSP etc, but we are unable to program the devices properly without the software hereby required.

Many thanks in advance for your time!

Ronald
Flash Arcade SARL
FRANCE

RE: TPA3255: TPA3255 FAULT_N signal goes low when using Power Resistors versus Speakers

Shenghao Ding — Sat, 31 Oct 2026 01:15:53 GMT

Short answer

Yes — resistive loads are a valid test load for the TPA3255. TI's own EVM documentation specifies speakers or resistor loads of 2–8 Ω at roughly 300 W for bench testing 1. The faults you are seeing point to the value and wiring of your resistor loads, not to resistors as a load type.

Most likely cause: you halved the load impedance

Amp	Driver load	Resistor load	Effect
Mono BTL (single 8 Ω driver)	8 Ω	4 Ω	2× current at the same output voltage; sits at the BTL minimum
PBTL (two parallel 8 Ω)	4 Ω	depends on how you wired the 4 Ω resistor(s)	2 Ω if you substituted one resistor per driver

TI specifies the TPA3255 BTL operating load range as 3.4–4 Ω and PBTL as 1.7–2 Ω, with PVDD operating limits that depend on load 2, and the family table lists 4 Ω as the minimum supported BTL load at up to 53.5 V 3. At max-volume electrical tests, a 4 Ω resistor on an amp designed around 8 Ω will drive output current toward the overcurrent threshold (typ. 17 A, programmable via the OC_ADJ resistor) 2, which pulls FAULT low. Operating below the specified load impedance or with insufficient output-filter inductance is a documented cause of overcurrent and DC-detect trips 4.

Action: use 8 Ω resistors for the BTL amp and a 4 Ω resistor for the PBTL amp — i.e., match the nominal driver impedance, not a lower value. Confirm each resistor's continuous power rating covers your max-volume test (~300 W class per the EVM guidance) 1.

Also verify (documented FAULT triggers)

Mode-pin vs. wiring consistency — a load across OUT_A/OUT_B is BTL wiring and must match the mode-pin configuration; SE settings with that connection fault immediately 5. Re-check that your test harness didn't change which output terminals are bridged.
No cross-amp output tying — connecting outputs of two amplifiers together is unsupported and can trip overcurrent even unloaded 6.
Bootstrap capacitance — the device samples MOSFET voltage during conduction to estimate current; insufficient bootstrap capacitance leaves the FET under-enhanced and produces false overcurrent trips 7. This shows up under the higher current a 4 Ω load demands, which is consistent with "only faults with resistors."
FAULT low covers overload, undervoltage, and overtemperature conditions — confirm which by reading CLIP_OTW alongside FAULT 8.

RESET_N going low — treat as a separate issue

Knowledge gap: the retrieved material does not establish a mechanism by which the TPA3255 itself drives RESET_N low, nor the associated timing. RESET_N is a device input, so something external (your controller, a supervisor, or a damaged pin) is pulling it. One documented failure mode is RESET_N damage from improper power sequencing or 0 Ω connections from an early-rising 3.3 V rail to configuration pins; substituting 10 kΩ series resistors stopped the recurrence in that design 9. Also note RESET/FAULT/CLIP_OTW pins are rated for 9 mA max continuous sink and −0.3 to 4.2 V 2 — verify your test instrumentation isn't loading them.

Scope your debug: scope RESET_N, FAULT, PVDD and GVDD together on the 2 s failure to determine whether RESET_N drops before or after the audio stops.

Follow up: Want help interpreting your FAULT/CLIP_OTW state combination to isolate whether the trip is overcurrent, DC detect, or overtemperature?

TPA3255: TPA3255 FAULT_N signal goes low when using Power Resistors versus Speakers

John Pierson — Fri, 30 Oct 2026 20:53:13 GMT

Part Number: TPA3255

We have a working design with two TPA3255DDV Amplifiers. One is configured as PBTL and supports low and mid frequencies with two parallel 8 Ohm drivers. Thie other amp is configured Mono BTL with a single 8 Ohm driver. For testing reasons, I have tried to use 4 Ohm Wire Wound Power resistors instead of drivers. This causes the FAULTn signal to go low. Also on power up, I sometimes see RESETn go low after about 2 s of output audio and audio stops. I do not see the FAULTn or RESETn signal go low on power up when we use drivers versus power resistors.

Can power resistors be used for testing purposes like max volume electrical tests?

TPA3255: TPA3255DDVR Amp DVDD

Mark Sampson — Fri, 30 Oct 2026 17:00:22 GMT

Part Number: TPA3255

We have seen a few TPA3255DDVR that failed in the field and the DVDD (pin 11) was shorted to GND. Can you have me undersand based on the internal layout of the chip what might cause this and how I could recreate it in the lab.

RE: TPA3255: TPA3255DDVR Amp DVDD

Shenghao Ding — Sat, 31 Oct 2026 01:15:27 GMT

Upfront knowledge gap

TI's public documentation does not disclose the transistor-level internal structure of the DVDD regulator, so the exact die-level failure path for a pin-11-to-GND short cannot be established from available material. What follows is what the documentation and reported field/lab cases do support.

What pin 11 actually is

DVDD (pin 11) is the output of an internal LDO linear regulator fed from VDD, brought out only for an external bypass capacitor 1. It is not a supply input.
It regulates to approximately 3.3 V and is not adjustable 2.
Absolute maximum DVDD-to-GND is −0.3 V to 4.2 V 3.
The datasheet explicitly states the AVDD/DVDD regulators are sized only for internal circuitry and must not power external loads; added loading causes voltage sag and noise injection 1.
Importantly, the device's documented protection (output short-circuit, overtemperature, undervoltage, POR) covers output pins and fault conditions — there is no protection for a DVDD overstress or short 4.

Interpretation: a hard DVDD-to-GND short is a post-damage symptom — the LDO pass device or the digital circuitry it feeds has been destroyed, leaving a low-impedance path. It is the result of electrical overstress, not a cause in itself.

Documented overstress mechanisms consistent with your symptom

Mechanism	Evidence
Back-driving configuration pins from a live external 3.3 V rail through 0 Ω while PVDD/GVDD are off. Applying 3.3 V to M2 and FREQ_ADJ through 0 Ω before PVDD/GVDD drove high current into those pins and destroyed multiple devices; changing to 10 kΩ eliminated failures across 20 units 5	Strongest documented match — this is a sequencing/pre-bias fault that injects current into the internal digital domain that DVDD supplies
VDD overvoltage. VDD maximum is 4 V; direct application of 12 V is identified as potentially immediately damaging 2	Overstressing the LDO input
Exceeding the 4.2 V DVDD absolute max — stresses beyond absolute maximum may cause permanent device damage 3	Direct
Grounding integrity. Poor PVDD-section ground connectivity and incorrect interconnection of PCOM/ACOM/DCOM were identified as a board-level fault mechanism; normal operation resumed once grounds were solidly tied 2	Ground bounce shifts the internal digital reference
Inadequate decoupling / power routing. The datasheet warns incorrect power routing, connection, or decoupling can cause reduced performance, errant functionality, or damage 1	Requires 10 µF + 0.1 µF on VDD 6
Probing-induced transients. One design reported multiple failures after probing the internal AVDD node, though TI noted routine probing does not normally damage the part — not established as root cause 2	Weak/inconclusive

A near-identical field signature has been reported: DVDD collapsed to ~0.8 V with VDD still at 12 V, external back-driving of DVDD did not restore function, and only IC replacement fixed the board 7. A pin-11-to-GND short has also been reported independently 8.

Lab reproduction

Rank these by how well they match the documented evidence:

1. Pre-power-up pin injection (highest-confidence reproduction)
Replace any series resistors on M1/M2/M3/FREQ_ADJ/RESET with 0 Ω, bring up your system 3.3 V logic rail first with PVDD and GVDD off, hold that state, then apply PVDD. This is the exact condition that destroyed multiple devices in the field; monitor current into the configuration pins during the sequence 5. Then repeat with 10 kΩ to confirm the mitigation.

2. VDD / DVDD overvoltage
Ramp VDD above its 4 V maximum 2, or force DVDD above 4.2 V from an external current-limited source 3. Note: TI documentation does not specify a safe current limit or an approved DVDD-stress procedure, so set the limit conservatively and treat parts as scrap.

3. Ground-path degradation
Deliberately open or high-impedance the PCOM/ACOM/DCOM interconnect on a test board to replicate the reported grounding fault 2. Ground pins are 12, 13, 25, 26, 33, 34, 41, 42 6.

Distinguishing a real short from a fault state: shorting DVDD to GND on a healthy part produces a POR/undervoltage fault that is self-clearing with outputs in Hi-Z and recovers once DVDD rises 9. Your field units show a permanent low impedance that survives removal of the stress — that distinction is the test for confirming you have reproduced the actual failure rather than a transient fault.

Recommended next step for your field units

Since no public documentation establishes the die-level mechanism, submit two or three of the failed TPA3255DDVR units to TI for formal failure analysis. FA can identify the actual damage site (LDO pass device vs. downstream digital), which the available documentation cannot.

Follow up: Would you like help reviewing your power-up sequencing and configuration-pin resistor values against the datasheet-recommended startup conditions to check whether your design is exposed to the pre-bias mechanism above?

Citations

RE: TAD5242: TAD5242 Power-Up/Power-Down Sequence: DIN State Before Power-Up and BCLK High State During Power-Down

Garret Godfrey — Fri, 30 Oct 2026 19:33:03 GMT

Hi Kyohei-san,

No, no difference in BCLK input circuitry should explain this difference. So there is a standard logic device between the MCU and DAC? Is it the same device before the TAD5142 and the TAD5242? Why does BCLK go high again after being driven low initially?

The recommended method is to drive the BCLK low from the MCU before powering down the DAC.

Best,

Garret

TAD5242: TAD5242 Power-Up/Power-Down Sequence: DIN State Before Power-Up and BCLK High State During Power-Down

Kyohei — Fri, 23 Oct 2026 04:20:55 GMT

Part Number: TAD5242

Hi team,

Our customer is currently evaluating the TAD5242 and has some questions regarding the power supply sequencing requirements.

During their evaluation, they observed some conditions related to DIN and BCLK during power-up and power-down.

We would appreciate your clarification on the following three points.

1. Is DIN included in "ASI Clocks"?

According to the datasheet, DIN is described as the audio serial data interface bus input, while BCLK is the bit clock and FSYNC is the frame synchronization signal.

Could you please confirm whether DIN is included in the term "ASI Clocks" used in the power supply sequencing requirements, or whether "ASI Clocks" refers only to clock-related signals such as BCLK and FSYNC?

2. Is it acceptable for DIN to be High before the TAD5242 is powered on?

During the customer's evaluation, DIN may already be at a High level before AVDD/IOVDD of the TAD5242 are powered on.

The datasheet specifies the absolute maximum rating for the digital input voltage as:

Digital input voltage: -0.3 V to IOVDD + 0.3 V

Therefore, could you please confirm whether applying a High level to DIN while IOVDD = 0 V is allowed?

If it is allowed, could you also provide the allowable input voltage and/or injection current under this condition?

3. Is it acceptable for BCLK to remain High during the power-down sequence?

During the customer's evaluation, they observed that BCLK remains continuously High for approximately 1 second during power-down when the TAD5242 is connected.

When the TAD5242 is disconnected, this High condition does not occur.

Because of this behavior, the customer is concerned about whether the specified power-down sequence timing requirement of 10 ms or more can be satisfied.

Could you please clarify the following points?

Does "ASI clocks stopped" mean that there must be no clock transitions, regardless of whether BCLK remains High or Low?
Is it acceptable for BCLK to remain continuously High for approximately 1 second during power-down?
Does BCLK need to be driven Low before AVDD/IOVDD are turned off?

If necessary for further investigation, we can provide the waveforms measured during the customer's evaluation via private message.

Thank you for your support.

Best regards,

Kyohei

RE: TLV320AIC3254: audio codec processing capability

Garret Godfrey — Fri, 30 Oct 2026 19:07:35 GMT

Hello,

Our expert on this device is out of office, please allow our team until next week to respond.

Best,

Garret

TLV320AIC3254: audio codec processing capability

Henry Wang3 — Fri, 30 Oct 2026 10:59:40 GMT

Part Number: TLV320AIC3254

Hi Sir,

My customer is currently evaluating whether the TLV320AIC3254 meets their requirement for an audio codec with DSP functionality in their DSC products. Could you please help confirm if the following features are supported?

Application: DSC
Input: 2x PDM DMICs (Stereo) | SNR: 64 dBA | Sensitivity: -26 dBFS
Output: 1x Speaker (0.4W, 10phi)
* Note: The audio output can also be processed by the SoC to support USB UAC (USB Audio Class) output.

I. miniDSP Customization:
Can the TLV320AIC3254's built-in miniDSP be programmed to customize the processing block routing sequence for input audio, as shown in the diagram below?

II. DMIC Input Audio Processing:
1. Input Level Adjustment (ADJ)
After the DMIC input, can the TLV320AIC3254 adjust the input signal level prior to audio processing to optimize the signal?

2. Sound Quality Correction (EQ)
Regarding the Low-Cut Filter (LCF) / High-Pass Filter applied to the input audio signal: Can the filter be configured as a 1st-order filter? Can the cutoff frequency be set to 100Hz?

3. Noise Reduction (NR)
Can Wind Noise Reduction (WNR) be implemented using the built-in DSP?

4. Level Adjustment (LEVEL)
Can the output level be adjusted via Gain Control with configurable ranges and step sizes?
Can the left and right channels be adjusted synchronously (stereo-linked) to prevent stereo image shift?
When the input volume is too high, can AGC or a Limiter be applied to prevent output clipping?

5. Automatic Gain Control (AGC)
Can the AGC compress the dynamic range of the microphone input signal without causing unnatural audio artifacts, while raising the average volume to improve audibility?
Do the static characteristics include Limiter, Compressor, and Expander (Noise Gate) functions, and do the dynamic characteristics include Attack and Release settings?
If the built-in AGC is insufficient, can additional DSP blocks be implemented to supplement it?

III. Speaker Output Audio Processing:
1. LR MIX
Can the stereo audio be mixed down to mono, and can this routing be restricted specifically to the media playback path?

2. EQ
Can a Parametric EQ or IIR Filter be used to adjust the frequency response of the output audio?
Is it possible to configure separate EQ parameters for media playback, camera operation sounds, and UI/operation sounds?

3. Volume Adjustment (LEVEL)
Can independent volume settings for different audio sources be achieved via software control or parameter switching?

4. AGC
Can AGC processing be applied to the mono audio after the LR MIX?
Are the AGC parameters adjustable (e.g., Thresholds for the Limiter/Compressor/Expander, Ratio/Slope for the Compressor/Expander, and Attack/Release times)?

IV. DMIC SNR Performance:
Is it possible to improve the DMIC SNR performance to >45 dBA?

V. Stereo DMIC Placement:
Regarding the stereo DMIC L/R inputs, is there a recommended placement distance (spacing) between the left and right DMICs to achieve an optimal stereo image when using the integrated audio codec?

VI. USB Audio Routing:
Can the audio output also be routed through the SoC to support USB UAC (USB Audio Class) output?

RE: NE5532: Authenticity Verification

Carrie — Fri, 30 Oct 2026 17:17:52 GMT

Hello,

Yes, the device is authentic. This particular lot is from August 2025. Please let me know if you have further questions.

Best regards.
Carrie

NE5532: Authenticity Verification

user5883945 — Fri, 30 Oct 2026 10:18:48 GMT

Part Number: NE5532

Dears,

The project is urgent, and the customer has purchased some samples from the market. The top side and wafer appearance pictures are as follows. Can we determine the authenticity?

TLV320DAC3100: Schematic review

Kavin R — Fri, 30 Oct 2026 11:23:21 GMT

Part Number: TLV320DAC3100

Hi TI,

Please review the schematic attached below and let me know your comments.

RE: TLV320DAC3100: Schematic review

Arash Loloee — Fri, 30 Oct 2026 15:55:24 GMT

Hello Kavin, Overall it looks fine to me.

I like to add 22 to 100Ohm series resistors to I2S lines.

I see a zero ohm resistors at the HPL and HPR pins . Note the HPL/HPR outputs are biased at a programmable common-mode voltage not at ground (CM is set to 1.35 V, 1.5 V, 1.65 V, or 1.8 V by changing register 31 in page 1 , bits D4–D3), so an ac-coupling capacitor (dc-blocking) should be connected between the device output pins and the headphones. Please refer to section 6.3.10.12.1 Headphone Drivers

Regards,

Arash

RE: TAS2505: TAS2505IRGER LDO_SEL pin no longer in datasheet

Shenghao Ding — Fri, 30 Oct 2026 14:41:35 GMT

Short answer

Your power-up failure is a known TAS2505 internal-LDO defect, not a board issue. TI removed the internal-LDO content from the datasheet because a functionality problem could trap some TAS2505 devices in a power-on-reset loop under specific device and power-supply combinations — which matches your symptom exactly (boots fine once LDO_SEL is no longer pulled to SPKVDD) 1.

Why the docs disagree

Item	What it says	Why
Datasheet (LDO removed, LDO_SEL → GND)	LDO_SEL listed as an input, "Connect to ground"; LDO registers marked reserved 2	Reflects the de-recommendation workaround after the POR-loop defect was found. TI noted the registers themselves remain active 3
Application Reference Guide	Internal LDO enabled by driving LDO_SEL to SPKVDD; AVDD (LDO output) tied externally to DVDD 4	Describes the architectural feature; was not updated in step with the datasheet

The silicon defect was corrected by a change to the internal LDO, planned for Rev.C production material 1. TI has since confirmed the integrated LDO can be used with material marked Rev.C, and that the datasheet limitation would be corrected 5.

⚠️ Flagged conflict: the datasheet revision history states Rev. D fixed an erratum involving the LDO_SEL feature, and that Rev. C had removed the LDO/LDO_SEL references 6 — the opposite of the ordering you describe, while the Rev. D pin table still says "Connect to ground" 2. The document set is internally inconsistent; I cannot resolve which wording TI intends as final.

Can you use the internal LDO?

It depends on your device material revision, not the datasheet revision.

Affected (pre-fix) material — your observed behavior indicates this. Use external AVDD and DVDD supplies and tie LDO_SEL low. When the LDO is disabled, AVDD and DVDD are tri-stated and must be externally powered 4.
Rev.C-marked material — the integrated LDO is usable 5.

If you use the internal LDO, the documented requirements are:
- LDO_SEL driven to SPKVDD; input 2.7–5.5 V
- AVDD (the LDO output) must be externally wired to DVDD to supply both rails
- ≤50 mA combined load, ≥300 mV dropout, ≥1 µF decoupling on both AVDD and DVDD 4

Note on your pull-up resistor: the documentation shows LDO_SEL driven/tied directly to SPKVDD, not through a pull-up. The retrieved material does not specify an acceptable series resistance for this pin, so I can't confirm whether your resistor value is itself a contributing factor independent of the silicon defect.

Regardless of LDO configuration

Page 1, Register 2, Bit 3 must still be written to power up the PLL and headphone level shifters — this applies to both internal- and external-LDO configurations 3.

Recommended next step

Read the revision marking on your TAS2505IRGER units and confirm with TI whether your date-code/lot is pre- or post-LDO-fix material. That single data point determines whether you can re-enable the internal LDO or must commit to external AVDD/DVDD rails.

TAS2505: TAS2505IRGER LDO_SEL pin no longer in datasheet

F van Ommen — Fri, 30 Oct 2026 09:59:46 GMT

Part Number: TAS2505

Dear,

The Rev.D version of the datasheet mentions nothing anymore regarding the internal LDO functionality other than to connect the LDO_SEL pin to GND.

Comparing this to Rev.C and the TAS2505 Application Reference Guide (Rev. D) (which has its latest revision October 2026) these mention that the internal LDO can be used and enabled by connecting LDO_SEL to SPKVDD.

We have designed it with a pullup resistor betweel LDO_SEL and SPKVDD, but this is giving us power up issues. When removing this pullup resistor, our device suddenly boots OK.

Why is all reference removed in Rev.D of the datasheet? And why is it then still mentioned in the Application Guide?

Can we still use the internal LDO?

KR,

Ferris

TPA3130D2: consumption

Jeff YANG — Fri, 30 Oct 2026 04:26:37 GMT

Part Number: TPA3130D2

Hi team,

I have a few questions regarding the power consumption of the TPA3130D2DAPR:

Is the IC's current consumption primarily determined and calculated based on the specifications and power of the backend load (speaker)?
If the PVCC supply is 15V, and both left and right channels are connected to an 8ohm 15W speaker respectively, would the current consumption of the IC be approximately 2A?

thanks!

Jeff

RE: TPA3130D2: consumption

Shenghao Ding — Fri, 30 Oct 2026 14:40:54 GMT

Hi Jeff,

Yes — supply current scales with the output power delivered to the speaker load, following approximately I_PVCC ≈ P_OUT/(η·PVCC), plus quiescent current. 1
For two 8 Ω channels at 15 W each (30 W total) at 15 V PVCC, the ideal supply current even at 100% efficiency would be 2.0 A, so real current must exceed 2.0 A once efficiency losses are included. 2 The datasheet confirms 2×15 W into 8 Ω BTL at 15 V is within spec and lists 90% typical efficiency, 3 but the actual efficiency curve value at this specific output level isn't resolved in the retrieved data, so an exact current figure can't be confirmed yet.

To pin down the precise current draw, I'd need:
- The datasheet's efficiency-vs-output-power curve value at 15 V/8 Ω/15 W per channel (the curve exists but wasn't numerically extracted).
- Confirmation of whether your use case involves continuous full-power (worst-case thermal/current) or average music-program power, since quiescent (20 mA at 12 V) and full-load current differ significantly. 4

Follow up: Would you like me to pull the exact efficiency percentage from the datasheet's BTL efficiency-vs-power curve at the 15 W/8 Ω operating point so the current estimate can be refined further?

TAS67534-Q1: Sampling Frequency

kenji gemma — Wed, 28 Oct 2026 05:52:58 GMT

Part Number: TAS67534-Q1

Hello, Team,

Please give us some advice.
The latest datasheet for the TAS67534-Q1 includes the following description in the “Startup Script” section:

Please explain the contents of this section in more detail.
This is because we cannot understand the details based on the comments alone.

This is not mentioned in the Startup-Script for TAS67524-Q1; please also explain why.

Best Regards,
Kenji Gemma

RE: TAS67534-Q1: Sampling Frequency

Dylan Yao — Fri, 30 Oct 2026 12:59:07 GMT

Kenji,

The pass produced silicon are the same.

[quote userid="461440" url="~/support/audio-group/audio/f/audio-forum/1693248/tas67534-q1-sampling-frequency/6525742"]Q:Are the hardware specifications of the prototype and mass-produced versions of the device the same?[/quote]

Yes, it can be applied to prototype device. While please make sure the device is final version silicon, it can be confirmed by below reading method

w e0 00 00 # Page 0

w e0 7F 00 # Book 0

w e0 7D 11 # Enter setup mode

w e0 7E FF # Enter setup mode

w e0 00 02 # Page switching to page 2

r w0 00 0E # Read 0x0E register, if it is 0x41, it is final silicon

w e0 00 00 # Page switching to page 0 (00)

w e0 7D 00 # Exit setup mode

w e0 7E 00 # Exit setup mode

[quote userid="461440" url="~/support/audio-group/audio/f/audio-forum/1693248/tas67534-q1-sampling-frequency/6525742"]Q:Would it be okay to apply this script to a prototype of the device?[/quote]

Dylan

RE: TAS6424-Q1: Mute delay time

Dylan Yao — Fri, 30 Oct 2026 12:50:21 GMT

Jinkai,

Mute pin toggle High->Low and I2C Mute command function are the same, they have same duration of mute time.

Dylan

TAS6424-Q1: Mute delay time

Daniel Wang (auto) — Wed, 28 Oct 2026 03:54:10 GMT

Part Number: TAS6424-Q1

Hi team,

Customer is building an plaftform in which TAS6424L-Q1 is used.

They wangt to know what is the responding time of MUTE pin (from signal trigger to actual Mute) ? And what is the Mute consuming time via I2C?

BR,

Daniel