Audio forum - Recent Threads

TAS2505-Q1: Unintended Tick Sound Observed

Ahmed Alaa — Mon, 25 May 2026 19:45:16 GMT

Part Number: TAS2505-Q1

Hello TI Team,

We are currently working on the STLA Digital Cluster project utilizing the TAS2505-Q1 audio amplifier. We are encountering a specific audio artifact (a sharp "tick") during chime playback and are reaching out for configuration guidance to resolve this at the hardware level.

Below is a summary of our system architecture, the issue, and the testing we have conducted so far.

1. System & Audio Architecture

SoC: R-Car Gen3 (M3N)
Audio Format: 16-bit PCM (Signed, Little-Endian) converted from a 16 kHz Mono source to a 44.1 kHz Stereo .raw file.
SSI / I2S Configuration: 64-bit frame ("16 bits data + 16 bits padding" per channel).
Actual Hardware Clocks: Due to internal SoC clocking limitations, our actual measured clocks deviate slightly from the 44.1 kHz standard:
- BCLK: 2.777777 MHz
- WCLK: 43.402777 kHz

2. Amplifier Configuration

We have attached our full TAS2505 initialization script Amp_cfg.txt for your review . Please note that immediately before playback, we dynamically adjust the gain registers to the following states:

Page 0, Reg 65 (0x41): 0xE8
Page 1, Reg 46 (0x2E): 0x00

3. Issue Description & Observations

While streaming the audio, we hear a sharp "tick" sound in the middle of the playback.

We conducted the following tests to isolate the issue:

Volume Boost: We analyzed the source 16 kHz mono .wav file using a Web-based audio engine. At standard volume, it plays perfectly. However, when applying a 150% volume boost to the mono file, the exact same "tick" appears. When testing our upsampled 44.1 kHz stereo file, the tick appears at a 210% boost.
FFmpeg Normalization (Limiter): We regenerated the raw file using FFmpeg, applying a digital audio limiter to specifically compress that rogue peak (limiting to 90%) without changing the master volume.
- Result: Playing this limited file on our cluster completely eliminated the tick.

Kindly we need your support to understand the issue in more detail and try to find a solution using some configuration in the Amplifier.

Thank you for your support and insights.

RE: TAS2505-Q1: Unintended Tick Sound Observed

Kevin Lu — Wed, 03 Jun 2026 02:13:25 GMT

Hi Ahmed,

Good Catch, 1-cycle clock shift error will cause twice of amplitude, pls make sure your input signal format is 100% match to the amp setting

Best Regards

Kevin

TLV320AIC3109-Q1: How should the audio link be written?

lllya02 Ffff — Wed, 03 Jun 2026 01:52:03 GMT

Part Number: TLV320AIC3109-Q1

This is the schematic of my audio system. Please ignore the input labeled es8388, as it has not been updated yet. Regarding the mic, in the driver I only found SND_SOC_DAPM_INPUT("MIC1LP"); SND_SOC_DAPM_INPUT("MIC1RP"); SND_SOC_DAPM_INPUT("MIC1LM"); but the hardware shows MIC1LP/LINE1LP, MIC1LM/LINE1LM, MIC2P/LINE2P, MIC2M/LINE2M. Could you tell me how I should write my device tree link, or do I need to make changes to the driver?

PCM1798: I/V converter connected to the PCM1798 output

Hidetaka Iganami — Tue, 02 Jun 2026 08:10:26 GMT

Part Number: PCM1798

I am considering using the PCM1798 in a system without a negative power supply.
In the reference circuit, the I/V converter is designed to use both positive and negative power supplies.
Is it possible to design a version that uses only the positive power supply?

RE: PCM1798: I/V converter connected to the PCM1798 output

Hidetaka Iganami — Wed, 03 Jun 2026 01:36:48 GMT

In the reference circuit, the non-inverting input of the op-amp used for the I/V converter is connected to GND.
Is it possible to operate an op-amp of I/V converter by applying a bias positive voltage to its non-inverting input so that its output is positive?

PCM1798: Feasibility of single-supply 9-V I/V stage with 4.5-V virtual reference

Ryu Yamashita — Wed, 03 Jun 2026 01:29:19 GMT

Part Number: PCM1798

Hi team,

Background: We are evaluating PCM1798DBR for an audio design. The target is to reduce power-supply cost by using a single 9-V supply for the external I/V amplifier, with a 4.5-V reference applied to the op amp non-inverting input instead of the GND-referenced I/V stage shown in the datasheet/reference circuits. The PCM1798 analog supply remains 5 V and digital supply 3.3 V.

Questions:

Is it acceptable to operate the PCM1798 current output pins with the I/V summing node biased around 4.5 V, rather than held near GND? Please provide the allowable IOUT compliance/common-mode voltage range, if specified.
If this topology is acceptable, what Rf range and op amp input/output swing requirements are recommended to avoid clipping and THD+N/SNR degradation, considering the 4 mAp-p full-scale current and 3.5 mA center current?
If not recommended, is the official recommendation to use a split supply for the I/V stage, such as ±5 V, or to select a voltage-output DAC?

Requests: Please provide an official recommendation and any relevant reference circuits, application notes, or E2E guidance for PCM1798 single-supply I/V conversion.

Best Regards,

Ryu.

TAS2120EVM: TAS2120EVM AMPS231C User Guide

Shannon Tan — Thu, 28 May 2026 06:06:31 GMT

Part Number: TAS2120EVM

Hello,

It appears that the TAS2120EVM user guide is based on a different revision of the board than the one I received. I have misplaced the document that came with the kit itself---would it be possible to get access to information on how to configure and bring up the TAS2120EVM AMPS231C board?

For reference, the user guide selection jumpers are completely header based---for my board, SEL5, 4, and 3 are all switches rather than headers.

Thank you!

RE: TAS2120EVM: TAS2120EVM AMPS231C User Guide

Shannon Tan — Wed, 03 Jun 2026 01:12:06 GMT

Yes, I got everything configured as much as I am aware of, and tested both 0000 and 0001 for SW5. Unfortunately, I am encountering an issue with PPC3, as it says "Connected EVM is not valid for this app. Please connect a valid EVM."

As for the jumpers on the bottom side of the board, please see the attached image:

I have tested this configuration with both 3.3V and 1.8V IOVDD, both do not work. I have also removed the two SDA and SCL jumpers (maybe they were pull-ups?) and as expected it did not resolve the issue.

One interesting thing of note is that when I press the SDZ button, the power draw of the speaker jumps from 44mW to 125mW. Not sure if this is relevant.

Please let me know if you need any other information.

TAS2574EVM: PPC3 SW doesn't recognize TAS2574 EVM

Doug Peeler — Tue, 28 Apr 2026 16:56:06 GMT

Part Number: TAS2574EVM

I am setting up my TS2574EVM for the first time. I downloaded latest PPC3 (v3.3.0) and installed the 257x EVM v3.0.0. Upon attaching the USB cable from the host PC to the AC-MB and launching the 257xEVM App in PPC3, I get an error message stating that "The connected EVM is not valid for this app. Please connect a valid EVM." Note that the PPC3 console detected my approved EVM SW after logging into my account. I am assuming this was the correct App for the EVM. However, I don't know how to confirm if it is correct or if there is some other jumper setting on the EVM HW itself. Any ideas on how to connect?

RE: TAS2574EVM: PPC3 SW doesn't recognize TAS2574 EVM

Shenghao Ding — Tue, 02 Jun 2026 21:44:31 GMT

Congratulations! May I close this thread?

TAC5112: Fine adjustment PLL - TAC5112 as I2S/TDM controller

Kristoffer Skoeien — Tue, 02 Jun 2026 14:06:37 GMT

Part Number: TAC5112

This discussion continues from: https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1588417/tac5112-is-the-pll-adjustable/6177621

If the TAC5112 is configured as I2S/TDM controller/master. How large changes can be done to the PLL before one can witness adverse affects?

To describe the scenario: We have a master timing device. In order for us to keep clocks in sync, we need to fine-tune the TAC5112 PLL runtime.
Turning the device off/muting etc., making adjustments and turning on/unmute is not an option.

- We have read the documentation, but no limits can be found. Do you have any guidelines? (Max PLL ppm/% change/second or similar).
- Would any adjustments be ok, as long as we monitor that the PLL does not unlock?

The help is greatly appreciated.

Kind regards
Kristoffer

RE: TAC5112: Fine adjustment PLL - TAC5112 as I2S/TDM controller

Mir Jeffres — Tue, 02 Jun 2026 21:15:02 GMT

Hi Kristoffer,

Since we last messaged on here, my app note that goes into more detail about the PLL and clock tree has been released: https://www.ti.com/lit/an/slaaep0/slaaep0.pdf

I give some more ranges to keep the internal clocks inside of. If your changes allow the internal clocks to be within ~5% of their expected value as specified in the app note, then it should continue to work. You may get pops and clicks in the audio when you adjust the clock since there may be sudden changes in the samples timing. I would recommend that you do check the PLL lock interrupts, but if the PLL becomes "unlocked" the audio will likely stop.

Best,
Mir

RE: TAS2505-Q1: Unintended Tick Sound Observed

Ahmed Alaa — Tue, 02 Jun 2026 20:45:39 GMT

Hi Kevin,

We have an exciting update: We found the root cause of the audio "tick," and the issue is now fully resolved.

Following our last observation where we captured maximum I2S values of 15403 and -16506, we discovered a protocol alignment mismatch between the SoC and the Amplifier.

The SoC was transmitting data in Left-Justified format, but the TAS2505 was initialized to expect standard I2S format.

Here is exactly how this caused the issue:

Because I2S expects a 1-clock cycle delay after the Word Select (WS) edge, the TAS2505 was sampling the data one bit late.
This 1-bit offset caused the amplifier to drop the Most Significant Bit (the Sign Bit) and read the 2nd bit as the new MSB.
On our loudest negative peak of -16,506 (Binary: 1011 1111 1000 0110), dropping the leading 1 and reading the next 0 as the sign bit forced a severe integer wrap-around. The amplifier interpreted the data as 0111 1111 0000 1100, which equals +32,524.
This instantaneous phase inversion from a large negative voltage to a massive positive voltage is exactly what drove the "tick" on the speaker.

After updating the TAS2505 Audio Interface Setting Register (Page 0, Register 27) to match the Left-Justified format, the amplifier is now reading the true Sign Bit. The chime plays flawlessly at maximum volume with zero ticks or distortion.

Thank you again for your time and support during our debugging process!

Best regards

RE: TAS2505-Q1: Unintended Tick Sound Observed

Ahmed Alaa — Tue, 02 Jun 2026 19:24:27 GMT

Hello Kevin,

I checked the output I2S Data from the SOC to the Amplifier using an Oscilloscope, and checked maximum values and they were 15403 and -16506 as shown in images. Could you please check and guide us to what to check next?

RE: TAC5112: Distortion when after disabling and re-enabling DAC

Garret Godfrey — Tue, 02 Jun 2026 19:12:12 GMT

Hi Christina,

Do you have a before/after scope shot of the DAC output? How are you measuring the distortion?

I ran your script on EVM, and the DAC output reappears as normal after the mute/unmute cycle.

Best,

Garret

TAC5112: Distortion when after disabling and re-enabling DAC

Christina Lim — Tue, 02 Jun 2026 07:49:36 GMT

Part Number: TAC5112

Hi,

My customer is observing distortion when using a specific sequence sequence to disable and then enable the DAC. Can you help advice?

Audio Codec TAC5112 hardware design and register settings are as follows:

* IOVDD uses 1.8V and AVDD uses 3.3V.

IN1P: MIC1 single ended input (TX TDM slot 4, 16 bits 8KHz)

IN1M: MIC2 GND

IN2P: MIC2 single ended input (TX TDM slot 6, 16 bits 8KHz)

IN2M: MIC2 GND

Out1P/M: differential spk out (RX TDM slot 4, 16 bits 8KHz)

Out2P/M: differential earpiece (RX TDM slot 6,16 bits 8KHz)

w a0 00 00
w a0 01 01
w a0 02 0B
w a0 06 30
w a0 0A 00
w a0 11 80
w a0 10 50
w a0 1A 00
w a0 1B 00
W a0 1C 00
w a0 1E 24
w a0 1F 26
w a0 26 00
w a0 28 24
w a0 29 26
w a0 37 20
W a0 43 00
w a0 4B 00
w a0 4D 00
w a0 50 50
w a0 52 A1
w a0 53 80
w a0 55 50
w a0 57 A1
w a0 58 80
w a0 5B 00
w a0 5F 00
w a0 64 20
w a0 65 20
w a0 66 20
w a0 67 C9
w a0 68 80
w a0 69 C9
w a0 6A 80
w a0 6B 20
w a0 6C 60
w a0 6D 60
w a0 6E C9
w a0 6F 80
w a0 70 C9
w a0 71 80
w a0 72 18
w a0 73 10
w a0 76 CC
w a0 77 20
w a0 78 E0

Why do I observe distortion when I follow the sequence below to disable and then enable the DAC, Please advise.

Disable SPK out:
w a0 00 00

w a0 67 00

Then only

w a0 76 C0

Enable SPK out:
w a0 00 00

w a0 76 CC

then only

w a0 67 C9

Disable earpiece:
w a0 00 00

w a0 6e 00

Then only

w a0 76 C0

Enable earpiece:
w a0 00 00

w a0 76 CC

then only

w a0 6e C9

Thansk,

Christina

RE: TAS2574EVM: PPC3 SW doesn't recognize TAS2574 EVM

Doug Peeler — Tue, 02 Jun 2026 18:53:02 GMT

Ran the SW I2C Logger. I reconnected everything. Connected to the I2C Master module, went to the Log tab, clicked on the Green light to make it Red, ran the command, and this was the result of the Log: w a1 00 00 54 41 53 32 35 37 34 2d 45 56 4d 00 52 45 56 2d 41 00 53 2f 4e 2d 30 30 30 30

TLV320AIC3007: Regarding the handling of ground (GND) in the TLV320AIC3007 PCB layout.

Boris liu — Fri, 29 May 2026 09:44:18 GMT

Part Number: TLV320AIC3007

HI TEAMS.

We are currently using the TLV320AIC3007 for audio circuit design. According to TI’s documentation for the TLV320AIC3007EVM‑K, the ground is divided into DGND (digital ground), AGND (analog ground), and SPGND (power ground).
How should these three grounds be handled in the PCB layout?Since the PDF images do not clearly show the layout details, could you please explain in detail how the grounding should be arranged on the PCB?

In addition, in another third‑party design, the ground is divided into digital ground and analog ground, while the power ground is merged with the analog ground.
Is it acceptable to reference this approach for our PCB grounding design? Thank you.

RE: TLV320AIC3007: Regarding the handling of ground (GND) in the TLV320AIC3007 PCB layout.

Jeff McPherson — Tue, 02 Jun 2026 18:47:23 GMT

Hi Boris,

Please look in the zip file. TI uses mostly Altium designs and the files included are compatible with Altium.

Impedance matching is not required anywhere for this design.

Length matching is helpful for digital signal buses such as I2C / I2S. It is also a good idea to length match differential input pairs if your analog inputs are differential.

For width based of power consumption you can design for the following rules of thumb. These are not reflective of actual power draw, but are estimates including headroom to ensure you trace will have enough current capacity in any end case

AVDD_xx + DRVDD = 20mA (3.3V)

IDVDD = 10mA (1.8V)

Best regards,
Jeff McPherson

PCMD3180: PCMD3180 Linear Phase Filter does not cut high frequencies correctly

Machate Michael — Mon, 11 May 2026 15:59:18 GMT

Part Number: PCMD3180

Hi,

We measured the transfer function of the linear filter in frequency domain. Unfortunaly we can see Aliasing Effects. The cut of frequency is not correct. I can you provide the measurements offline. Please send my your email contact.

RE: PCMD3180: PCMD3180 Linear Phase Filter does not cut high frequencies correctly

Garret Godfrey — Tue, 02 Jun 2026 17:38:11 GMT

Thank you. Will close over email

TAS3251: One phase of TAS3251 in BTL mode doesn't work properly

user4991603 — Tue, 02 Jun 2026 10:20:37 GMT

Part Number: TAS3251

Hello,

in the current production run we have a higher number of TAS3251 that don't work properly and I'm looking for a clue what might be the problem and I'm seeking for advice if there is something I could further measure.

In no load condition one phase doesn't switch with a duty cycle of 50%.

In all cases the output switches to ground for a much shorter period so that the produced DC offset is much higher than half the supply voltage.

There is no short on the outputs. Might there be a problem with one of the MOSFETs on the output?

Could the Bootstrap capacitor be a problem?

The current setting resistor has a correct value of 27k.

The AMP Error signal is low so the amp recognizes that something is wrong.

Do you might have a hint for me what I could further check?

Best regards,

Stephan

RE: TAS3251: One phase of TAS3251 in BTL mode doesn't work properly

Isaac Buliva — Tue, 02 Jun 2026 16:21:31 GMT

Hi Stephan,

As long as you followed the datasheet recommendation for 33nF bootstrap capacitors with a rating of at least 25V and placed them close to the pins to minimize trace length, there should be no problem there. The fault that you are seeing could be caused by either a overtemperature, overcurrent or undervoltage event. You mentioned you are using a 27kΩ OC_ADJ Resistor Value which corresponds to a OC threshold of 13.5A, I would check to ensure your output current is not exceeding this value.

Regards,

Isaac

RE: TAC5112: TAC5112: Fine adjustment of clocks - TAC5112 as I2S/TDM target

Garret Godfrey — Tue, 02 Jun 2026 16:20:21 GMT

Hi Kristoffer,

The device can tolerate around 1% clock jitter. The clock errors can be unmasked in Page 0x01, INT_MASK0 register 0x2F and read in Page 0x01, INT_LTCH0 register 0x34.

There are also Page 0x00 CLK_ERR_STS registers 0x3C-0x3D for more detailed clock error status.

Best,

Garret

TAC5112: TAC5112: Fine adjustment of clocks - TAC5112 as I2S/TDM target

Kristoffer Skoeien — Tue, 02 Jun 2026 14:20:45 GMT

Part Number: TAC5112

This question is closely linked to https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1588417/tac5112-is-the-pll-adjustable/6177621.

If we have a TAC5112 running as I2S/TDM target/slave:

How large perturbations can be accepted on the BLCK/FSYNC/MCLK lines?

In short, the I2S/TDM controller will have some variablilty in the clock outputs, and we want to make sure we are within spec. I could not find any such figure in the datasheet.
And/or, is there any way we can detect that the TAC5112 is having issues processing data if the clock variations are too large?