Audio forum - Recent Threads

TAS5830: TAS5830 ppc tools request

jp liu — Wed, 16 Sep 2026 06:00:48 GMT

Part Number: TAS5830

TAS5830 ppc tools request

TAS5827: Hardware control mode

Koshi Ninomiya — Wed, 16 Sep 2026 05:26:00 GMT

Part Number: TAS5827

Dear Team,

My customer is considering to use the TAS5827RHBR in their system.
They would like to know about the hardware control mode.
If they want to input audio signals in TDM mode, can they use hardware control mode?
Or are there any restrictions in the hardware control mode, such as that it can only support I2S?

Best Regards,

Koshi Ninomiya

TAS5822MEVM: TAS5822M-SW / PPC3 Plugin access request approval

Byoung-Soo Je — Tue, 08 Sep 2026 23:48:29 GMT

Part Number: TAS5822MEVM

Hi TI Team,
I have purchased the TAS5822MEVM board for evaluation.
I requested access for TAS5822M-SW several days ago, but the status is still Pending.
Could you please check and approve access for my account (bs.je@samsung.com)?
Thank you!

RE: TAS5822MEVM: TAS5822M-SW / PPC3 Plugin access request approval

Wenbin Li1 — Wed, 16 Sep 2026 03:18:29 GMT

Hi Byoung-Soo Je,

my colleague had approved it. I will close this thread.

Br,

Wenbin

RE: TAS2781EVM: TAS2781 EVM Outputs Loud Noise Instead of Normal Audio After Writing PPC3-Generated CFG via I2C Tool

Wenbin Li1 — Wed, 16 Sep 2026 03:09:07 GMT

Hi Keith,

the PPC3 version seems correct. I upload the full output of the integration. please try to get it. I compress it to 7z format.

e2e.ti.com/.../tas2781_5F00_test_5F00_bin.7z

Br,

Wenbin

TAS2781EVM: TAS2781 EVM Outputs Loud Noise Instead of Normal Audio After Writing PPC3-Generated CFG via I2C Tool

Keith Yang — Tue, 25 Aug 2026 05:38:48 GMT

Part Number: TAS2781EVM

Dear All

Currently I am encountering an issue when using the TAS2781 EVM. After configuring and tuning the EVM with PPC3, the EVM can output sound normally. However, when I write the CFG file generated by PPC3, such as combined_configuration_0_ClassH_TuningMode.cfg, to the EVM using an I2C master tool within PPC3, the EVM does not output sound normally and instead produces loud noise. What could be the reason for this? The screenshot below shows the version information of the PPC3 I am using.

RE: TLV320AIC3104: Can the AGC be frozen?

Martin Alcock — Wed, 16 Sep 2026 00:01:33 GMT

Thanks, we may be able to make that work. The only thing that stands out is that the AGC gain register (32) is from -12 to +59.5dB, where as the PGA gain is 0 to 59.5dB, leaving out the attenuation values. We will have to experiment with it.

Thanks for your help.

TLV320AIC3104: Can the AGC be frozen?

Martin Alcock — Tue, 15 Sep 2026 00:12:36 GMT

Part Number: TLV320AIC3104

I am working on a communications system that uses this part and the AGC. A transmitting station prefixes its transmission with a tone leader, that is used by the receiver for adjusting its AGC. However, after the leader is the data portion, where we do NOT want the AGC to adjust. Is there a way to freeze it at its current setting, and determine if it has stopped adjusting?

Thanks.

RE: TLV320AIC3104: Can the AGC be frozen?

Mir Jeffres — Tue, 15 Sep 2026 23:43:10 GMT

You would need to implement your own logic to do this, since we do not have a simple register to set to pause the AGC. However here is what I would suggest:

1) check the current AGC applied gain (reg 32)
2) set PGA gain to the same value as current AGC applied (reg 15)
3) disable AGC (reg 26)

Make sure these writes are sequential to help avoid a pop if gains changed too slowly and the AGC then adjusted before you turn it off.

RE: TLV320AIC3104: Can the AGC be frozen?

Martin Alcock — Tue, 15 Sep 2026 23:29:30 GMT

Still need to know how to freeze it at the current setting.

RE: TLV320AIC3104: Can the AGC be frozen?

Mir Jeffres — Tue, 15 Sep 2026 23:29:06 GMT

Sorry, updated above. Let me know what you think.

RE: TLV320AIC3104: Can the AGC be frozen?

Martin Alcock — Tue, 15 Sep 2026 23:28:22 GMT

Yes??

RE: TLV320AIC3104: Can the AGC be frozen?

Mir Jeffres — Tue, 15 Sep 2026 23:23:13 GMT

Hi Martin,

There are a few things to check here. First, the AGC does have a live interrupt that flags when the input is above the noise threshold, so this will tell you if the AGC is active or not, this is in page 0 register 36. Then, you can read the AGC applied gain setting on registers 32 and 33.

Best,
Mir

TAC5212: No audio from right channel with 4 ohm speaker (continued due to TI system error)

De Bug — Sat, 12 Sep 2026 02:49:41 GMT

Part Number: TAC5212

Continued from [mention:fac23b3eded04b849425e53ca5aa3a7c:46448885d0e64133bbfbf0cd7b0fd6f7] (UNRESOLVED)

As posting reply always results in an error and to contact the webmaster (without any link how..)

---

Sorry, yes, RX digital data to the CODEC from Soc.

I only use amixer and alsamixer to change the outputs config, with line-out differential both OUT1 and OUT2 have signals on P and M pin, but with speaker and headphone "stereo" not. The expected use case with "stereo"is Left on OUT1P and right on OUT1N, Either speaker, line or headphone, and OUT1 and 2 can be individually set for either. but still retaining the option to change to differential line out

for OUT1(L)+2(R) via amixer, i thing that are very normal cases for audio systems. Indeed, I2S input has always channels via FCLK, so I understand in this stereo mode they both carry the same audio data. That is very common for multiple audio outputs on PC's as well.

-- TI website issue

P.S I wonder when TI is going to fix this forum softwar ?

1. submitted this 4 times and every time it does not save an
2. Often posts are not fully shown, files contents and attachment not shown
3. reply button not working not showing text box
4. using F5 refresh sometimes get it right mostly not, theb

5. I need to reconfirm I am human. Half hour spend I need to confirm 4 to 5 times I am human.
6. Creating a support request in TO, it does not save it
7. Trying to escalate to get help, TI says cases cannot be escalated

8. even when having a session, sometimes need to re-login again

9. when informing TI of these issues, that ticket get closed w/o any actions.

Please look into this

RE: TAC5212: No audio from right channel with 4 ohm speaker (continued due to TI system error)

Garret Godfrey — Tue, 15 Sep 2026 21:33:29 GMT

Hi De Bug,

This could be an issue with how the SOC sends the data. I2S only supports 2 channels, yet you have the audio bus set up like this:

In the register dumps, the codec is configured in differential output mode, which means the DAC only outputs channel 1 (OUT1P/M) and channel 2 (OUT2P/M). In this case, any digital data in Left Slot-1 and Right Slot-1 would be ignored at the analog output.

I could not see any scope shots of the data being sent, but it is possible that the data is sent incorrectly somehow such that there is not any data output to Channel 2. Could you share a schematic?

Best,

Garret

PCMD3140: PCMD3140: capture-start-latched modulo-4 phase state produces an in-band (−1)^n self-image (carrier exactly Fs/2) — deterministic reproducer available

Lorenzo Pecci — Mon, 10 Aug 2026 07:12:33 GMT

Part Number: PCMD3140

Hi,

we are seeing a start-latched signal-corruption state on the PCMD3140 (STM32MP2 host, codec is ASI slave, DSP_B TDM 4×32, BCLK 128×fs = 6.144 MHz, auto clock config, PLL on, two PDM mics sharing PDMDIN1 on opposite PDMCLK edges, CH1/CH2, PDMCLK 3.072 MHz).

Symptom (quantified). On a fraction of capture starts, each channel's output contains an additive linear self-image: y[n] = x[n] + eps * s * (-1)^n * (h conv x)[n], where the modulation carrier sits at exactly Fs/2 (24000.0 Hz within one FFT bin), s = +/-1 and is identical on both channels within a given capture, eps is about 0.5 at 10 kHz, and |H| rises with frequency. In the spectrum, the 12-16 kHz band is a mirrored copy of the 8-12 kHz band folded around Fs/4 - i.e. the exact signature reported (and never root-caused) in thread 1014760, where a sine at Fs/4 comes out amplitude-modulated.

What we established experimentally (a demodulated-coherence detector gives a clean binary verdict in ~4 s of ambient noise; happy to share data):

The state is latched at capture start and is perfectly stable for ≥180 s.
Four phase states exist (cross-spectrum phase 0/180° or ±90° depending on register write order): 2 clean, 2 bad. It is a modulo-4 divider/commutator phase latch.
With auto clock config + PLL at BCLK=128×fs the landing is random, ~50% clean.
Every deterministic configuration lands on a BAD phase: PLL disabled (AUTO_MODE_PLL_DIS, BCLK 256×fs) → 24/24 bad; auto clock + PLL at BCLK=256×fs → 24/24 bad. This gives us a 100% reproducer.
All of the following have NO effect on the latched phase (tested on the deterministic reproducer and/or N=24 statistics at 128×fs): BIQUAD_CFG (DSP_CFG1 0x6C = 0x40/0x20/ 0x00 — we tried your 8-mic fix from thread 1644894), decimation-filter mode, channel summing, PDMCLK_DIV (0.768/1.536/3.072/6.144 MHz), PDMDIN edge select, phase calibration (register 0x7B and CHx_PCAL), keeping PLL_PDZ powered across sessions, PWR_CFG power-up ordering per datasheet 7.4.2, BCLK polarity inversion (consistently on both bus sides), and ~70 PWR_CFG/SLEEP power-bounce cycles over I²C with clocks running (those re-roll the state but ONLY between the two bad positions — never clean).
The state re-rolls ONLY when BCLK/FSYNC (re)start. Register content is identical between clean and bad captures (full page-0 hardware readback).

Questions:

Is the start phase of the decimator/output-stage clock divider chain relative to FSYNC specified/deterministic? Our data says it latches one of 4 positions at clock appearance and only the PLL path randomizes it.
Is there an undocumented register write (page 0/1, or the CLKGEN_CFG mentioned in the VAD_CFG1 custom-clock description but absent from the register map) that resets or selects this phase — the way DSP_CFG1=0x20 fixes the known 8-mic latency issue on PCMD3180?
If manual clock configuration (AUTO_CLK_CFG=1) is the intended path: what is the full register recipe for fs=48 kHz, BCLK=128×fs slave mode? With MST_CFG0=0x42 + MST_CFG1=0x46 alone the output is corrupted, and PPC3 does not document what else it writes.
Is there errata for this behavior? Thread 1014760 shows the same signature in 2020.

We can run any register sequence you suggest against the 100% reproducer and report within minutes. Thanks!

RE: PCMD3140: PCMD3140: capture-start-latched modulo-4 phase state produces an in-band (−1)^n self-image (carrier exactly Fs/2) — deterministic reproducer available

Garret Godfrey — Tue, 15 Sep 2026 18:37:04 GMT

Hi Lorenzo,

Thank you for your detailed investigation and workaround. I will close the thread.

Best,

Garret

PCM6140-Q1: PCM6140 Channel Powered Down but everything else seem in order.

John Doe — Tue, 15 Sep 2026 09:40:04 GMT

Part Number: PCM6140-Q1

Hello,

I am trying to record audio from 4 differential analog microphones using a PCM6140 on an embedded device that communicates with the PCM through I2C. This connection is working properly, the device does ACK and reading back from registers shows my config is sent properly. The device is working in target mode and receives a BCLK at 6.144MHz and FSYNC at 48kHz (ASI_STS register shows that FSYNC and fs_ratio is are properly detected). The device outputs in TDM (4 channels) with word length of 32 bits per sample. The four input channels are enabled as well as the four ASI output channels. The ADC_PDZ bit is enabled as well as the PLL_PDZ bit. The INT register shows no interrupt on both ASI and PLL.

The power supply AVDD and IOVDD are good as well as AREG, DREG, and VREF that match the values provided by the datasheet. The SHDNZ pin is pulled high.

The connected microphones are working properly and are powered up.

Still, DEV_STS_0 shows Channel Powered Down for all channels and DEV_STS_1 shows Active With All Channels Off.

I am following the procedure from the device's datasheet (SBASAU4) found at 9.2.1.2, I also tried some alterations but I still can't get the ADCs to output any data.

Thank you for your help !

RE: PCM6140-Q1: PCM6140 Channel Powered Down but everything else seem in order.

Garret Godfrey — Tue, 15 Sep 2026 18:34:41 GMT

Hi John,

Can you share the full register dump? Thank you!

Best,

Garret

TAS2563: TAS2563 DEQ is not applied with PPC3 generated binary

Fumiya Sano — Mon, 14 Sep 2026 06:02:32 GMT

Part Number: TAS2563

Hello.

We are using TAS2563 and trying to use the Dynamic EQ (DEQ) function configured in PurePath Console 3.

1. DEQ is not working with the PPC3-generated binary

We configured the DEQ parameters in PPC3 and generated a binary file for our product firmware.
The binary file is loaded to TAS2563 at startup, but the DEQ does not seem to be applied.

We confirmed acoustically that the resonance which should be suppressed by DEQ still occurs.

We also monitored the I2C communication from PPC3 and found that some DSP coefficient registers are changed when DEQ is enabled.
However, when we read the corresponding registers on our product, these values were all zero.

We manually wrote the same coefficient values observed in PPC3 to TAS2563 via I2C, but the DEQ behavior still did not change.

Are there any additional procedures required to enable DEQ, such as:

DSP program/configuration loading
coefficient update procedure
DSP state change
bank switching / coefficient swap
any required enable bit

Also, are there any known cases where DEQ settings configured in PPC3 are not included or applied correctly in the generated binary file?

2. Is there a register to enable/disable DEQ directly?

For debugging purposes, we can directly read and write TAS2563 registers through I2C.

Is there a register or DSP control that can directly enable or disable DEQ?

If so, could you provide the Book/Page/Register address and the required setting?

We would like to verify whether the DEQ processing itself is active independently of the PPC3-generated binary.

Best regards

Fumiya.

RE: TAS2563: TAS2563 DEQ is not applied with PPC3 generated binary

Isaac Buliva — Tue, 15 Sep 2026 17:48:04 GMT

Hi Fumiya,

I will review these files and will get back to you.

Regards,

Isaac

RE: TAS5830: TAS5830 Schematic

Isaac Buliva — Tue, 15 Sep 2026 15:20:35 GMT

Hi Switch,

The component values in the schematic are difficult to read, can you reupload this with a higher resolution PDF or include the BOM.

Regards,

Isaac

TAS5830: TAS5830 Schematic

switch — Tue, 15 Sep 2026 06:33:10 GMT

Part Number: TAS5830

Hi ti team,

The new project is using the TAS5830; please help review the attached schematic. Thanks!

TAS5830.pdf

RE: PCMD3140: PCMD3140: capture-start-latched modulo-4 phase state produces an in-band (−1)^n self-image (carrier exactly Fs/2) — deterministic reproducer available

Lorenzo Pecci — Tue, 15 Sep 2026 08:53:34 GMT

Hi Garret,

a short update to close this from our side: we found a workaround.

The bad state depends on how many input channels are enabled. Same board, same bus (slave, PLL from BCLK, DSP_B 4 x 32, 128 x fs), same DTS, only the driver's channel enable changed.

With IN_CH_EN = 0xE0, CH3 is a PDM channel on GPI2 whose data line is physically open on this board: it only carries silence, yet the two real mics on DIN1 stop landing in the mirrored state. The 0xE0 configuration has been in normal operation for five days with a spectral check at every recording start, and the bad state has not appeared once. With 0xC0 it re-rolls at every bus clock stop/start (60-80 % at 128 x fs, 100 % at 256 x fs), and nothing else we tried moves it: not the decimation filter selection, not either consistent BCLK polarity, not the VAD.

This may also explain why your EVM never shows it: as far as we can tell the EVM scripts enable all four channels, while our two-mic design enabled only CH1 and CH2. A two-channel PDM configuration landing on one of four decimator phases at start-up is not something we could find in the datasheet.

One correction on my side: some "bad" counts in my earlier messages were taken on a quiet input with a spectral-mirror metric that gives false positives on the PDM noise floor. The numbers above use a band-limited noise stimulus (6.5-12.8 kHz at the mics) plus a demodulated coherence check.

We are shipping with CH3 enabled and consider the issue closed for us. Thanks for your time on this.

Best regards,

Lorenzo

RE: TAS2563: TAS2563 DEQ is not applied with PPC3 generated binary

Fumiya Sano — Tue, 15 Sep 2026 08:01:56 GMT

Hi Isaac,

Thank you for your response.

I checked the readback immediately after manually writing the DEQ-related values.
The values were written successfully, and the readback showed exactly the same values that I wrote.

For example, before writing, Book 0 / Page 0x11 / Registers 0x60–0x73 were all 0x00.
After manually writing the values observed in the PPC3 I2C monitor, the readback was:

0x60–0x63: 01 A7 32 F3
0x64–0x67: 00 00 00 00
0x68–0x6B: FE 58 CD 0D
0x6C–0x6F: 7E 2C 79 3A
0x70–0x73: 83 4E 65 E7

However, even after writing these values, I could not observe any change in the DEQ behavior.

I understand from your comment that several registers are affected by DEQ, so writing only these values may not be sufficient.

I have attached the PPC3 project file and the generated header/cfg files as requested.
Could you please check whether the DEQ-related settings are correctly included in the generated files?

Regards,
Fumiya

e2e.ti.com/.../PPC_5F00_file_5F00_forTI_5F00_20260915.zip