Audio forum - Recent Threads

TAS2563: Slow Output Amplitude Ramp-Up After Playback Starts

Hitoki Ishikawa — Wed, 10 Jun 2026 23:58:09 GMT

Part Number: TAS2563

Hi Team,

We have completed the amplifier tuning and implemented the driver to operate the amplifier.

However, after playback starts, the output amplitude gradually increases instead of reaching the expected level immediately. Could you please advise on how to fix or reduce this slow ramp-up behavior?

I have attached an oscilloscope waveform captured at the start of playback using a 1 kHz, 0 dB sine wave.

We are using the driver provided in the following thread:
TAS2563: TAS2563 Linux driver request for Kernel 6.1 and RCA file generation tool

Best regards,

RE: TAS2563: Slow Output Amplitude Ramp-Up After Playback Starts

Hitoki Ishikawa — Tue, 16 Jun 2026 01:32:44 GMT

Hi Team,

Thank you for your advice.

I tried the dedicated bypass profile by setting:

tinymix "Speaker Profile Id" 5

In this bypass mode, the slow output amplitude ramp-up issue did not occur.
So the issue seems to occur only with the tuned/DSP profile.

Could you please advise what I should check next?

Best regards,

TPA3130D2EVM: EVM board file

Jeff YANG — Tue, 16 Jun 2026 01:27:51 GMT

Part Number: TPA3130D2EVM

Hi,

May I know is possible to provide TPA3130D2EVM oringinal board file to customer?

If yes, please send it to Ko, Zoe <zoe_ko@ti.com> or Jeff YC Yang <JeffYC.Yang@arrow.com>

Thanks!

Jeff

TAS6684-Q1: TAS6684 output sporadically does not come back after STBY is released

Stefan Strobel — Fri, 08 May 2026 11:03:08 GMT

Part Number: TAS6684-Q1

Hi everyone,

we are using the TAS6684 in a new design.

We are using the STBY pin to shutdown the audio played back from the amp in some situations.

I mentioned a weird behaviour when releasing the STBY pin when the Amp is loaded (4 Ohm impedance on all 4 channels, sine output with a fairly high load (>60W / channel)).

Most of the time the AMP comes back up playing audio on all channels as expected.

Sometimes only some channels (or one) resumes playing.

Sometimes no channel comes back up.

The PWM is still active, but there is no output.

There is no Fault stored in any of the registers (none of the fault or fault mem registers show anything).

The state reports show all Channels in Play mode.

Is there anything I am missing.

Is there a way to prevent this from happening or at least detect it and restart the amplifier?

Thanks for your support

Stefan

RE: TAS6684-Q1: TAS6684 output sporadically does not come back after STBY is released

Shadow He — Tue, 16 Jun 2026 01:09:07 GMT

Hi Stefan

By double check your initialization, there's another 2 register worth to have a try.

The Volume ramp down is possibly to create similar issue.

# Digital Volume Ramp up/down controls

w c0 44 27

w c0 45 f0

RE: AM62D-Q1: Regarding DMA on AM62D/A

O.H — Tue, 16 Jun 2026 00:03:26 GMT

Hi Shreyansh,

Sorry for late reply, and thank you for your supports.

[quote userid="514673" url="~/support/audio-group/audio/f/audio-forum/1650944/am62d-q1-regarding-dma-on-am62d-a/6379174"]Unfortunately, apart from TRM and the software, there aren't any other documentation available at the moment for DRU. I will check internally though if there exists anything else.[/quote]

We await further information.

[quote userid="514673" url="~/support/audio-group/audio/f/audio-forum/1650944/am62d-q1-regarding-dma-on-am62d-a/6379174"]There is no known errata related to DRU that I am aware of.[/quote][quote userid="514673" url="~/support/audio-group/audio/f/audio-forum/1650944/am62d-q1-regarding-dma-on-am62d-a/6379174"]Your understanding is correct regarding DRU being a C7x dedicated engine for faster data transfer. However, doing a transfer inside ISR is generally not recommended, considering DRU/DMA transfers are a blocking call, and such there is no benchmark available.[/quote]

I understood.

[quote userid="514673" url="~/support/audio-group/audio/f/audio-forum/1650944/am62d-q1-regarding-dma-on-am62d-a/6379174"]Not really, the TRs can be configured for non contiguous memory regions as well. I am still reviewing the application. Please correct me if I am wrong, but this is the only existing issue here, right?
[/quote]

Yes, This is the only issue at the moment. I will share any additional information we find.

Best regards,
O.H

AM62D-Q1: Regarding DMA on AM62D/A

O.H — Mon, 01 Jun 2026 08:11:39 GMT

Part Number: AM62D-Q1

Hi experts,

We are currently verifying DMA transfers between L2 and DDR on a C7x application.

The application used for this verification is a bare-metal application based on FreeRTOS SDK version 12.00.00, specifically the dmautils_autoinc_1d2d3d and swasrc_multichannel_playback examples.

We have confirmed that the DRU works correctly when it is operated by itself. However, when McASP is running and we perform a DMA transfer using the DRU inside the McASP receive interrupt handler, the EFR can only be read as 0 even after executing __get_indexed(__EFR, 0). As a result, the application cannot trap the DRU transfer completion event registered in the CLEC.

We have the following questions:

Although the TRM and C7X_SW include an overview of the DRU, is there any documentation that explains the DRU in more detail, including the differences from BCDMA/PKTDMA?
Are there any known errata related to DRU operation, such as DRU execution not being guaranteed within an interrupt context?
We checked both the device errata and the SDK errata, but could not find any applicable item.
When using BCDMA for DMA transfers inside an interrupt routine, we could not achieve performance comparable to QDMA on the C66 core of the 66AK2G12. Therefore, we are considering using the DRU instead.
Our understanding is that the DRU is a C7x-dedicated engine and is therefore capable of faster data transfers. Is this understanding correct, or is there any misunderstanding?

Best regards,
O.H

TLV320DAC3100: LTC and Revision Change

kok cweng ong — Fri, 12 Jun 2026 00:30:28 GMT

Part Number: TLV320DAC3100

Hi, is there revision changes between LTC 5CI and LTC 64I?

RE: TLV320DAC3100: LTC and Revision Change

kok cweng ong — Mon, 15 Jun 2026 23:57:01 GMT

Thanks for the confirmation.

TLV320AIC3107: Output level higher than AGC target gain setting

user1238011 — Thu, 14 May 2026 10:18:00 GMT

Part Number: TLV320AIC3107

Hi,

The issue concerns the AGC function of the TLV320AIC3107.
The output level is higher than the configured target gain value.

What could be the cause of this behavior?

Based on the AGC parameter settings, the expected output level should be 141 mVrms.
However, the actual measured output is 294 mVrms, which is approximately 6 dB higher.

A difference of around 1 dB could be considered acceptable error, but 6 dB seems too large.

Input conditions and results:
1.Input signal: 133 mVrms
2.Output signal: 294 mVrms
3.Expected output signal: 141 mVrms
(Full scale = 0.707 Vrms, therefore -14 dB corresponds to 0.141 Vrms)

AGC parameters:
1.Target Gain: -14 dB
2.Max Gain Allowed: 59.5 dB

Other conditions:
1.The same result was obtained with both a 1 kHz sine wave input and pseudo-audio signals.
2.Signal path: LINE1LP (single-ended) input → I2S loopback → LEFT_LOP output
3.All internal gain settings are configured to 0 dB
4.Verified using the evaluation board
5.The output was measured with a high-impedance load.

Kind regards

RE: TLV320AIC3107: Output level higher than AGC target gain setting

Mir Jeffres — Mon, 15 Jun 2026 23:03:40 GMT

Hi,

No issues with leaving it open, just don't respond to this unless you do have a new question for me! I will update you here and you should get notified.

Best,
Mir

RE: TAS2572: How to add the IV-sense protection algorithm for TAS2572 on Qualcomm platform?

Shenghao Ding — Mon, 15 Jun 2026 22:41:04 GMT

Linux drivers are typically not designed to perform complex mathematical computations. They operate on the Application Processor (AP) rather than a Digital Signal Processor (DSP), focusing instead on hardware interaction, data transfer, and device control. Their primary role is to abstract hardware details and provide a standardized interface for the operating system and applications, ensuring efficient and reliable communication with peripheral devices.

As to algorithm, kindly consult algorithm owner.

TAS2572: How to add the IV-sense protection algorithm for TAS2572 on Qualcomm platform?

Terry Hu — Fri, 12 Jun 2026 06:17:59 GMT

Part Number: TAS2572

Hi team,

Please help to check below questions from customer.

The product uses a Qualcomm platform, and the TAS2572 driver selected is the RCA driver, which runs on the AP side (ARM). According to the previous support engineer’s explanation, this driver does not include speaker protection algorithms. The customer now requests the addition of the IV-sense protection algorithm. Should this protection algorithm run on the ADSP side or the AP side? Please help provide the relevant algorithm and porting documentation.

Best regards,

Terry

TLV320AIC3106: TLV320AIC3106 producing non-functional clks in 96khz

Sen Wang — Fri, 12 Jun 2026 02:04:02 GMT

Part Number: TLV320AIC3106

Hi experts,

I'm working on linux, and I have found an issue with TLV320AIC3106 on the AM62x/a/p/l-evms when generating bit clocks for 96khz audio. The configuration is as follows:

MCLK is 12.888Mhz
PLL disabled, with integer div Q = 2
Dual-rate mode (ADC oversampling = 64 rather than 128)

This affects 96khz audio (16/32 bit depth), theoertically it should also affect 64khz audio, although I have not tried it out.

The device datasheet didn't seem to mention any similar artifacts associate with the said configuration. The audio is working when I enabled PLL, although I'm not sure if it can generate the required clock, or is just playing equivalent of 48khz audio in disguise.

Any leads to this would be greatly appreicated. Ideally we need to resolve it for TLV320AIC3106 without creating regressions to the tlv320aic3x driver.

Best,

Sen Wang

RE: TLV320AIC3106: TLV320AIC3106 producing non-functional clks in 96khz

Mir Jeffres — Mon, 15 Jun 2026 21:17:56 GMT

Hi,

After trying your script and getting the same result, I see this part in the datasheet:

Confusing because it calls it "double-rate" mode instead of dual-rate, as it is otherwise referred to in the datasheet. So, there is no way to use CLKDIV for 96kHz sample rate without the PLL, as the extra division by 2 of the minimum Q value being 4 means that the dac_fs will be 24kHz, so doubling that sample rate will only get to 48k. Here is the script I used to verify, using your dump and adding comments, and then I also changed your gain settings to 0dB on the DAC:

w 30 01 80 #sw reset
w 30 07 80 #sw reset


w 30 00 00
w 30 01 00
w 30 02 00 #fsref/1
w 30 03 90 #pll enabled, q=2, p=8 -> SHOULD BE P = 1

# set PLL off and Q=4 (minimum for in dual rate mode)
w 30 03 21 #q=4, p=1

w 30 04 1c #j = 0111 = 7 = J
w 30 05 36 #00 1101 1010 1100 = 3500 = D
w 30 06 b0 # J.D = 7.35
w 30 07 6a #48k fsref, adc/dac dual rate enabled, l and r dac paths 
w 30 08 c0 #bclk and wclk are OUTPUT (master mode)
w 30 09 70 #dsp mode (tdm), 32 bit
w 30 0a 00 #0 offset
w 30 0b 01 #r = 1
w 30 0c 00 
w 30 0d 00
w 30 0e 00
w 30 0f 20 #ladc pga not muted, gain = 10 0000 = 16dB
w 30 10 20 #radc pga gain = 16dB
w 30 11 ff
w 30 12 ff
w 30 13 00 #line1l single ended, 0db gain to ladc pga mix, ladc powered down
w 30 14 78
w 30 15 78
w 30 16 00 #line1r single ended, 0db gain to radc pga mix, radc powered down
w 30 17 78
w 30 18 78
w 30 19 00 #micbias powered down
w 30 1a 00
w 30 1b fe
w 30 1c 00
w 30 1d 00
w 30 1e fe
w 30 1f 00
w 30 20 18
w 30 21 18
w 30 22 00
w 30 23 00
w 30 24 00 
w 30 25 c0 #l+r dac powered up
w 30 26 00
w 30 27 00
w 30 28 00
w 30 29 00 #dac_l1 and dac_r1 paths
w 30 2a 00
# w 30 2b 28 #ldac not muted, gain = -20dB
w 30 2b 00 #ldac not muted, gain = 0db

w 30 2c 28 #rdac not muted, gain = -20dB
w 30 2d 2f
w 30 2e 2f
w 30 2f af #dac_l1 routed to hplout, volume = -23.6dB
w 30 30 00
w 30 31 00
w 30 32 00
w 30 33 0d #hplout not muted, fully powered up, level = 0db
w 30 34 2f 
w 30 35 2f
w 30 36 af #dac_l1 routed to HPLCOM, volume = -23.6
w 30 37 00
w 30 38 00
w 30 39 00
w 30 3a 0d #hplcom not muted, fully powered up
w 30 3b 00
w 30 3c 00
w 30 3d 00
w 30 3e 2f
w 30 3f 2f
w 30 40 af #dac_r1 to hprout, volume = -23.6
w 30 41 0d #hprout notmuted, fully powered up
w 30 42 00
w 30 43 00
w 30 44 00
w 30 45 2f 
w 30 46 2f
w 30 47 af #dac_r1 routed to hprcom, volume = -23.6
w 30 48 0d #hprcom not muted, fuly powered up
w 30 49 2f
w 30 4a 2f
# w 30 4b af #dac_l1 routed to mono_lop/m, volume = same
w 30 4b 80 #volume = 0db

w 30 4c 2f
w 30 4d 2f
w 30 4e af #dac_r1 routed to mono_lop/m, volume = same
w 30 4f 09 #mono_lop/m not muted, fully powered up
w 30 50 2f
w 30 51 2f
# w 30 52 af #dac_l1 routed to left_lop, same vol
w 30 52 80 #volume = 0

w 30 53 00
w 30 54 00
w 30 55 00
w 30 56 09 #left_lop/m not muted, fully powered up
w 30 57 00
w 30 58 00
w 30 59 00
w 30 5a 2f
w 30 5b 2f
w 30 5c af #dac_r1 routed to right_lop/m, same vol
w 30 5d 09 #right_lop/m not muted, fully powered up
w 30 5e 00
w 30 5f 00
w 30 60 00
w 30 61 00
w 30 62 00
w 30 63 00
w 30 64 00
w 30 65 01 #codec_clkin uses clkdiv_out
w 30 66 02 #clkdiv_in uses mclk, pllclk_in uses mclk, ndiv = 2
w 30 67 00
w 30 68 00
w 30 69 00
w 30 6a 00
w 30 6b 00
w 30 6c 00
w 30 6d 00

Instead of CLKDIV, you will have to use the PLL. I see in your script that the PLL is currently set up for 44.1kHz mode, I would recommend using J.D = 8.0000.

I have been trying to get the PLL script working but for some reason the clocks coming out are different than I expect. I will try again tomorrow, unless you have a script that works for you with the PLL.

Best,
Mir

RE: PCM6260-Q1: how to best connect pcm6260 AVSS and VSS to the analog ground and digital ground on the board

Daveon Douglas — Mon, 15 Jun 2026 18:35:00 GMT

Hi Ming,

Can you explain the input architecture a little more?

The opamps on the analog front end are biased at VCC, so I assume the analog outputs have this bias from the op-amp. Then there is a second bias provided from the MICBIAS pin.

PCM6260 does not internally bias the input signal to an appropriate voltage common mode, so external biasing is required but only from one source.

PCM6260-Q1: how to best connect pcm6260 AVSS and VSS to the analog ground and digital ground on the board

MING GAO — Sun, 07 Jun 2026 09:35:20 GMT

Part Number: PCM6260-Q1

Our company's board design utilizes the PCM6260 and input operational amplifier,as well as the PCM1781 and output operational amplifier.I am struggling with how to connect the analog ground and digital ground.

Method 1:The analog part of the PCM6260 and the input operational amplifier are connected together with the analog part of the PCM1781 and the output operational amplifier as the analog ground,while the rest are used as digital ground.The analog ground and digital ground are connected together through a resistor under the VSS of the PCM6260.

Method 2 :The PCM6260 has a unified digital ground,with only the input operational amplifier connected together with the PCM1781 and operational amplifier.The analog ground and digital ground are connected together near the power supply.

could you help me :1.How is the best way to connect the analog ground and digital ground?

2.How should the AVSS and VSS of PCM6260 be connected?

TAS2110EVM: Missing TAS2110EVM app in PurePath Console 3

Marc Engineer — Mon, 15 Jun 2026 11:32:24 GMT

Part Number: TAS2110EVM

Unfortunately I can't find any option to install the TAS2110EVM GUI app within PurePath Console 3.

And the TI website only shows a button for requesting PurePath Console 3 itself, but not for the TAS2110EVM app.

RE: TAS2110EVM: Missing TAS2110EVM app in PurePath Console 3

Isaac Buliva — Mon, 15 Jun 2026 15:59:40 GMT

Hi Marc,

You can request access to the TAS2110EVM app here: https://www.ti.com/drr/opn/TAS2110-GUI.

For future reference, we have a device app lookup table available here: https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1395362/faq-purepathconsole-software-lookup-table-for-audio-devices.

Regards,

Isaac

RE: TAS5805MEVM: PUREPATHCONSOLE

Isaac Buliva — Mon, 15 Jun 2026 15:39:11 GMT

Hi Jeff,

The TAS5805MEVM PPC3 App is available here: https://www.ti.com/secureresources/TAS5805-SW.

Regards,

Isaac

TAS5805MEVM: PUREPATHCONSOLE

Jeff YANG — Mon, 15 Jun 2026 10:26:04 GMT

Part Number: TAS5805MEVM

Hi,

Does TAS5805MEVM using same PUREPATHCONSOLE GUI version for develop?

I've tested TAS5825P in the past, but seems the GUI have not show TAS5805MEVM selection in GUI page.

Thanks!

Jeff

TAA5242: Questions on clocking and I2S controller mode behavior of TAA5242

Ryu Yamashita — Fri, 12 Jun 2026 15:04:28 GMT

Part Number: TAA5242

Hi team,

Background:
We are evaluating the TAA5242 in Controller I2S mode with an external CCLK (24.576 MHz / 22.5792 MHz). We would like to confirm detailed behavior not fully clear from the datasheet.

Questions:

For MD2=High and MD1=Low in Controller I2S mode, what exact sampling rate (Fs) is generated for a given CCLK? Is Fs always 96 kHz with 24.576 MHz input?
Are FSYNC and DOUT both guaranteed to have the same output delay (e.g., max 19 ns) from BCLK falling edge?
In Controller I2S mode, does the device enter power-down solely based on the absence of CCLK?
When a clock error occurs (GPO interrupt), does ADC operation automatically resume once a valid CCLK is restored, or is a power cycle/reset required?

Best Regards,
Ryu.

RE: TAA5242: Questions on clocking and I2S controller mode behavior of TAA5242

Garret Godfrey — Mon, 15 Jun 2026 14:06:59 GMT

Hi Ryu-san,

A power reset is not required, but I would not change CCLK during operation. You must wait at least 100ms when stopping clocks to allow the device to complete the ADC shutdown sequence. I would stop CCLK, change the value, and wait 100ms before restoring the clock.

A clock error will appear on GPO that does require a power reset to clear, but does not affect operation.

Best,

Garret

TAD5112: TAD5112 cannot play 16-bit stereo

hangxiang guo — Fri, 12 Jun 2026 07:16:19 GMT

Part Number: TAD5112

When the TAD5112 is paired with a Jetson T4000 (link=dsp_a, slot=2, width=32), it can only play 32-bit stereo audio and cannot play 16-bit stereo audio (no sound on the second channel). The measured IIS waveform is correct.

RE: TAD5112: TAD5112 cannot play 16-bit stereo

Garret Godfrey — Mon, 15 Jun 2026 13:59:17 GMT

Hi Hangxiang,

In register 0x1A, you have set at 0x30, which is 32 bit slot width. This should be 0x00 for 16-bit data.

Best,

Garret