https://e2e.ti.com/support/audio-group/audio/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682119/tlv320aic3104-can-the-agc-be-frozen/6484620Wed, 16 Sep 2026 00:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:42fb788a-7af1-4b92-9724-f5f887bfe701Martin AlcockThanks, we may be able to make that work. The only thing that stands out is that the AGC gain register (32) is from -12 to +59.5dB, where as the PGA gain is 0 to 59.5dB, leaving out the attenuation values. We will have to experiment with it. Thanks for your help.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682119/tlv320aic3104-can-the-agc-be-frozen/6484609Tue, 15 Sep 2026 23:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5a061a4e-d16e-4f9e-92cc-6eb74bf903aeMir JeffresYou would need to implement your own logic to do this, since we do not have a simple register to set to pause the AGC. However here is what I would suggest: 1) check the current AGC applied gain (reg 32) 2) set PGA gain to the same value as current AGC applied (reg 15) 3) disable AGC (reg 26) Make sure these writes are sequential to help avoid a pop if gains changed too slowly and the AGC then adjusted before you turn it off.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682119/tlv320aic3104-can-the-agc-be-frozen/6484602Tue, 15 Sep 2026 23:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b05c9391-82ca-4153-9048-59aee279190dMartin AlcockStill need to know how to freeze it at the current setting.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682119/tlv320aic3104-can-the-agc-be-frozen/6484601Tue, 15 Sep 2026 23:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7b2f9905-6ad1-4ece-b1d6-7cf13e963373Mir JeffresSorry, updated above. Let me know what you think.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682119/tlv320aic3104-can-the-agc-be-frozen/6484599Tue, 15 Sep 2026 23:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:89044264-06fa-4984-ab54-d7f8850bac54Martin AlcockYes??https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682119/tlv320aic3104-can-the-agc-be-frozen/6484595Tue, 15 Sep 2026 23:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:149a4db7-7a17-428c-881d-fd4d3e1384bcMir JeffresHi Martin, There are a few things to check here. First, the AGC does have a live interrupt that flags when the input is above the noise threshold, so this will tell you if the AGC is active or not, this is in page 0 register 36. Then, you can read the AGC applied gain setting on registers 32 and 33. Best, Mirhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1681660/tac5212-no-audio-from-right-channel-with-4-ohm-speaker-continued-due-to-ti-system-error/6484496Tue, 15 Sep 2026 21:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8e4f7618-0bcf-44f3-9721-ada448d7e42fGarret GodfreyHi De Bug, This could be an issue with how the SOC sends the data. I2S only supports 2 channels, yet you have the audio bus set up like this: In the register dumps, the codec is configured in differential output mode, which means the DAC only outputs channel 1 (OUT1P/M) and channel 2 (OUT2P/M). In this case, any digital data in Left Slot-1 and Right Slot-1 would be ignored at the analog output. I could not see any scope shots of the data being sent, but it is possible that the data is sent incorrectly somehow such that there is not any data output to Channel 2. Could you share a schematic? Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1671802/pcmd3140-pcmd3140-capture-start-latched-modulo-4-phase-state-produces-an-in-band-1-n-self-image-carrier-exactly-fs-2-deterministic-reproducer-available/6484253Tue, 15 Sep 2026 18:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1e4af8ab-7580-4fa0-9aa0-1a77d91ae52aGarret GodfreyHi Lorenzo, Thank you for your detailed investigation and workaround. I will close the thread. Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682313/pcm6140-q1-pcm6140-channel-powered-down-but-everything-else-seem-in-order/6484246Tue, 15 Sep 2026 18:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bd2dc141-c3a6-4ead-8406-e289d955fb24Garret GodfreyHi John, Can you share the full register dump? Thank you! Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1681815/tas2563-tas2563-deq-is-not-applied-with-ppc3-generated-binary/6484190Tue, 15 Sep 2026 17:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2f78797a-5d8d-4f7f-94ce-46ff591a891dIsaac BulivaHi Fumiya, I will review these files and will get back to you. Regards, Isaachttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682217/tas5830-tas5830-schematic/6483995Tue, 15 Sep 2026 15:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5551f5b8-4512-406d-9110-d6aa9a538613Isaac BulivaHi Switch, The component values in the schematic are difficult to read, can you reupload this with a higher resolution PDF or include the BOM. Regards, Isaachttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682313/pcm6140-q1-pcm6140-channel-powered-down-but-everything-else-seem-in-orderTue, 15 Sep 2026 09:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8c0ccccc-431e-4e4d-983b-7fc97a25cf04John DoePart Number: PCM6140-Q1 Hello, I am trying to record audio from 4 differential analog microphones using a PCM6140 on an embedded device that communicates with the PCM through I2C. This connection is working properly, the device does ACK and reading back from registers shows my config is sent properly. The device is working in target mode and receives a BCLK at 6.144MHz and FSYNC at 48kHz (ASI_STS register shows that FSYNC and fs_ratio is are properly detected). The device outputs in TDM (4 channels) with word length of 32 bits per sample. The four input channels are enabled as well as the four ASI output channels. The ADC_PDZ bit is enabled as well as the PLL_PDZ bit. The INT register shows no interrupt on both ASI and PLL. The power supply AVDD and IOVDD are good as well as AREG, DREG, and VREF that match the values provided by the datasheet. The SHDNZ pin is pulled high. The connected microphones are working properly and are powered up. Still, DEV_STS_0 shows Channel Powered Down for all channels and DEV_STS_1 shows Active With All Channels Off. I am following the procedure from the device&#39;s datasheet (SBASAU4) found at 9.2.1.2, I also tried some alterations but I still can&#39;t get the ADCs to output any data. Thank you for your help !Portable ElectronicsPCM6140-Q1https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1671802/pcmd3140-pcmd3140-capture-start-latched-modulo-4-phase-state-produces-an-in-band-1-n-self-image-carrier-exactly-fs-2-deterministic-reproducer-available/6483574Tue, 15 Sep 2026 08:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4e0ee666-7563-4c11-9037-2702a394c68bLorenzo PecciHi Garret, a short update to close this from our side: we found a workaround. The bad state depends on how many input channels are enabled. Same board, same bus (slave, PLL from BCLK, DSP_B 4 x 32, 128 x fs), same DTS, only the driver&#39;s channel enable changed. With IN_CH_EN = 0xE0, CH3 is a PDM channel on GPI2 whose data line is physically open on this board: it only carries silence, yet the two real mics on DIN1 stop landing in the mirrored state. The 0xE0 configuration has been in normal operation for five days with a spectral check at every recording start, and the bad state has not appeared once. With 0xC0 it re-rolls at every bus clock stop/start (60-80 % at 128 x fs, 100 % at 256 x fs), and nothing else we tried moves it: not the decimation filter selection, not either consistent BCLK polarity, not the VAD. This may also explain why your EVM never shows it: as far as we can tell the EVM scripts enable all four channels, while our two-mic design enabled only CH1 and CH2. A two-channel PDM configuration landing on one of four decimator phases at start-up is not something we could find in the datasheet. One correction on my side: some &quot;bad&quot; counts in my earlier messages were taken on a quiet input with a spectral-mirror metric that gives false positives on the PDM noise floor. The numbers above use a band-limited noise stimulus (6.5-12.8 kHz at the mics) plus a demodulated coherence check. We are shipping with CH3 enabled and consider the issue closed for us. Thanks for your time on this. Best regards, Lorenzohttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1681815/tas2563-tas2563-deq-is-not-applied-with-ppc3-generated-binary/6483513Tue, 15 Sep 2026 08:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9982e743-964b-4a70-a084-4349afc949ebFumiya SanoHi Isaac, Thank you for your response. I checked the readback immediately after manually writing the DEQ-related values. The values were written successfully, and the readback showed exactly the same values that I wrote. For example, before writing, Book 0 / Page 0x11 / Registers 0x60–0x73 were all 0x00. After manually writing the values observed in the PPC3 I2C monitor, the readback was: 0x60–0x63: 01 A7 32 F3 0x64–0x67: 00 00 00 00 0x68–0x6B: FE 58 CD 0D 0x6C–0x6F: 7E 2C 79 3A 0x70–0x73: 83 4E 65 E7 However, even after writing these values, I could not observe any change in the DEQ behavior. I understand from your comment that several registers are affected by DEQ, so writing only these values may not be sufficient. I have attached the PPC3 project file and the generated header/cfg files as requested. Could you please check whether the DEQ-related settings are correctly included in the generated files? Regards, Fumiya e2e.ti.com/.../PPC_5F00_file_5F00_forTI_5F00_20260915.ziphttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682217/tas5830-tas5830-schematicTue, 15 Sep 2026 06:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d3b4c229-7252-4aff-92ed-c464450d4480switchPart Number: TAS5830 Hi ti team, The new project is using the TAS5830; please help review the attached schematic. Thanks! TAS5830.pdfTAS5830Home theater &amp; entertainmenthttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1681660/tac5212-no-audio-from-right-channel-with-4-ohm-speaker-continued-due-to-ti-system-error/6483169Tue, 15 Sep 2026 03:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a5a55279-b2ff-4164-b2ee-d23c2804302dDe BugI use two small 4Ohm 5W box speakers, each connected to GND and tip. The sound on left is clearly audible, not on right. After placing the ear to the right speaker, actually there is sound but very low. swapping follows the output, not the speaker.,I can&#39;t seem to measure any analog signal over both speakers with a scope when even the left has audio. Attached are the dumps of the clocks and I2C settings. audio with a headphone stereo single ended both channels sound fine, even though with little bass sound (the output have only a 1uF coupling cap) e2e.ti.com/.../4ohm-right-channel-audio-issue.ziphttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1681696/tpa3136d2-the-output-power-issue-for-tpa3136d2/6483142Tue, 15 Sep 2026 02:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:79d1bdd4-f8ae-4595-884d-21195ded3e0eWenbin Li1Hi Zhang Liang, from the datasheet, the BTL mode can support 4 ohm. but if you want to use BTL mode, the PVDD should be lower than 12V. in this case. the output power should be ok to support 2*10W from the experience. but there is no data listed in the datasheet. Br, Wenbinhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1681966/tas6424ms-q1-i2s-rise-fall-time-requirement/6483033Tue, 15 Sep 2026 00:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:26fd929c-4789-403e-bc36-d712c70261c8Shadow HeHi Kuramochi-san [quote userid=&quot;315483&quot; url=&quot;~/support/audio-group/audio/f/audio-forum/1681966/tas6424ms-q1-i2s-rise-fall-time-requirement&quot;] Then, we&#39;d like to make sure whether TI can guaranty that TAS6424M-Q1 can receive I2S input correctly if rise/fall time is 5ns or faster when the the other timing parameter satisfy min/Max requirement. Can we guarantee correct operation if rise/fall time is 5ns? [/quote] Yes, no concern about it. [quote userid=&quot;315483&quot; url=&quot;~/support/audio-group/audio/f/audio-forum/1681966/tas6424ms-q1-i2s-rise-fall-time-requirement&quot;]We suppose that typical is just nominal value so we worry that this device cannot receive I2S input correctly when rise/fall time is around 5ns due to device to device variation.[/quote] Keep Min value as 5ns is no problem.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1682119/tlv320aic3104-can-the-agc-be-frozenTue, 15 Sep 2026 00:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9ed6e554-8c37-4677-abd8-78ed9960ca58Martin AlcockPart Number: TLV320AIC3104 I am working on a communications system that uses this part and the AGC. A transmitting station prefixes its transmission with a tone leader, that is used by the receiver for adjusting its AGC. However, after the leader is the data portion, where we do NOT want the AGC to adjust. Is there a way to freeze it at its current setting, and determine if it has stopped adjusting? Thanks.TLV320AIC3104https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1681629/opa1622-dac-output-stage-for-combined-line-out-and-headphone-output/6482941Mon, 14 Sep 2026 22:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7dd6d746-9452-4c6c-b508-1456b7ce8133Chris FeatherstoneHi Daniel, We have a document below that shows a filter stage. https://www.ti.com/lit/an/sbaa333a/sbaa333a.pdf?ts=1789425163434&amp;ref_url=https%253A%252F%252Fwww.google.com%252F Does this help? Best Regards, Chris Featherstone