https://e2e.ti.com/support/audio-group/audio/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669000/tas2780-tas2780-tdm-sdout-alignment-issue-with-32-bit-tdm8-and-iv-sense-data-transmission/6438414Tue, 04 Aug 2026 01:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f7e9a242-7cbd-45f2-b6b1-c3486b66de86Ben ChiangThe speaker voltage sense and current sense sample streams are 16-bit, so they always use two TX time slots. Our interface uses a 32-bit word length, but the maximum TX data width is only 24 bits. In this case, are the remaining 8 bits simply padded with zeros?https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1670008/tlv320dac3100-tlv320dac3100irhbr---application-issuesTue, 04 Aug 2026 01:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c934df7b-8730-4efd-b0ae-bc8a1feefe8ewei huPart Number: TLV320DAC3100 Dear TI Team, Excuse me! Please find attached information regarding a suspected application issue recently encountered by our company. ABA cross-verification indicates it is related to failed ICs, but no defects have been found on the desoldered components themselves. No failure modes can be observed on the failed ICs directly. The only symptom is that the buzzer produces no sound when the IC is mounted on our test station circuit. Our team is still investigating the root cause. Could you please help check whether there are potential risks in our circuit design or production process that may cause IC failures? Alternatively, can we send the ICs to you for analysis and confirmation? fa new form-TI-TLV320DAC3100IRHBR.docTLV320DAC3100Applianceshttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669973/tlv320dac3203-tlv320dac3203-headset-detect-and-mfp3-gpi-both-read-a-fixed-state-required-external-circuit-for-hp-detectMon, 03 Aug 2026 19:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fad82f31-88f6-47bc-ad98-a2f9ea44c680Kushal KirpalaniPart Number: TLV320DAC3203 Part: TLV320DAC3203 (RGE, 24-pin VQFN) Documents used: SLOS756B (Dec 2018), SLAU434A (Feb 2019) WHAT WE ARE TRYING TO DO Detect 3.5 mm headphone insertion and removal, so that firmware can switch the audio output between an external speaker amplifier and the DAC&#39;s headphone drivers. HARDWARE - The HP_DETECT net has exactly two nodes: U6 pin 6 (DMDIN/MFP3/SCLK) and pin 4 of the 3.5 mm jack (PJ-320A), which the schematic labels R2. - There is no pull-up, pull-down or series component anywhere on this net. (Schematic section attached.) - Jack pin 1 (S) = GND, pin 2 (T) = HPL via 47 uF, pin 3 (R1) = HPR via 47 uF. - Supplies: LDOIN/HPVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, AVDD = 1.8 V supplied externally with the internal AVDD LDO disabled. - SPI_SELECT = 0 (I2C control). No secondary serial functions and no digital microphone are used. MFP4 is not connected to the jack. - Clocking: no MCLK. The DAC is a slave and self-clocks from BCLK through the PLL at 44.1 kHz. QUESTIONS 1. What external circuit does the headset detect function require on MFP3? Neither SLOS756B section 8.2 nor SLAU434A shows a detect connection - the typical application wires the jack with only HPL, HPR and GND. Does the detect input provide an internal bias or current source, or must the board supply a pull-up and a switched contact to ground? 2. Is there any internal pull-up, pull-down or termination on MFP3? Neither document mentions one. If the pin is left open, what level do the detect block and the GPI bit report? 3. With detect enabled, Page 0 Reg 67 D6-D5 reads 01 (&quot;Stereo Headset detected&quot;) unconditionally, with or without a plug inserted. What conditions produce a fixed type flag like this? 4. With MFP3 configured as General Purpose Input, Page 0 Reg 56 D0 reads 0 unconditionally, with or without a plug, over 90 s of continuous polling. Is there any condition under which D0 does not reflect the actual pin level while D2-D1 = 10? 5. Does sampling of Reg 56 D0 require the codec to be clocked? We poll in both states - fully clocked (PLL locked, audio playing) and completely unclocked (no BCLK, PLL off) - and read 0 in both. 6. What is the maximum recommended pull-up resistance for MFP3? SLOS756B section 6.10 specifies VIH = 0.7 x IOVDD at IIH = 5 uA, which implies about 198 kohm or less at IOVDD = 3.3 V. Is 5 uA the actual worst-case input leakage, and is that table valid at IOVDD = 3.3 V, given that it is characterised at 1.8 V? 7. Is tying the detect input to the R2 contact of a 4-pole jack a supported arrangement, relying on a 3-pole plug&#39;s sleeve shorting R2 to ground on insertion? Or does TI expect a dedicated mechanical switch contact? FIRMWARE - EXACT REGISTER WRITES All writes are on Page 0 (Reg 0x00 = 0x00). A software reset (Reg 0x01 = 0x01) with a 10 ms settle precedes each configuration. Approach A - headset detect block (per SLAU434A Table 2-2, option W6): Reg 0x38 (56) = 0x00 ; D2-D1 = 00, MFP3 = Headset Detect Input Reg 0x43 (67) = 0x90 ; D7 = 1 enable, D4-D2 = 100 (256 ms debounce) read Reg 0x43 ; D6-D5 always returns 01 Approach B - MFP3 as General Purpose Input (option L6): Reg 0x38 (56) = 0x04 ; D2-D1 = 10, MFP3 = General Purpose Input Reg 0x43 (67) = 0x10 ; D7 = 0, detect block disabled read Reg 0x38 ; D0 always returns 0 In Approach B we read D2-D1 back on every poll and it consistently reads 10, so the pin is confirmed to still be configured as a GPI when D0 is sampled. OBSERVATIONS Condition Reg 56 D0 Reg 56 D2-D1 ------------------------------------------ ----------- ------------ No plug, unclocked, 90 s continuous poll 0 throughout 10 No plug, clocked (PLL locked) 0 10 Plug inserted, clocked, playing, 190 s 0 throughout 10 Two different headsets were tested. I2C is healthy: all reads return without error, and every other register on the device behaves normally (audio plays correctly through HPL and HPR). The only deviation ever observed was a single sample reading 1, captured at the instant a plug was physically withdrawn. It did not persist.tlv320dac3203Portable Electronicshttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669889/tlv320aic3110-tlv320aic3110---external-filter-circuits/6438019Mon, 03 Aug 2026 18:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:604f2670-443a-4327-9967-c34a650322efArash LoloeeHi , you can always use the USERS GUIDE as circuit reference as it has the needed component and values and even layout of the EVM used for testing the part. If a device doesn&#39;t have a UG, usually you can use the UG of a similar part. For example for this part you can use the following circuit. https://www.ti.com/lit/ug/slau285/slau285.pdf?ts=1785772178579&amp;ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLV320AIC3111 Also you can refer to the following app note as a reference for EMI Filtering on Speaker Outputs for this device in specific. https://www.ti.com/lit/an/slaa495/slaa495.pdf Regards, Arashhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669869/tlv320aic3100-tlv320aic3100---reset-gpio-and-i2s-voltage-group/6438016Mon, 03 Aug 2026 18:45:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:93843f79-06f3-4a4b-93d8-ec5cf191afeaArash LoloeeHello, All voltage information -along with max and min of each pin- usually is presented in different tables in datasheets such as &quot; Recommended Operating Conditions&quot; and &quot;Absolute Maximum Ratings&quot; or &quot; Electrical Characteristics&quot; Also l the range of supply voltages are mentioned in the first page of almost all datasheets (here is a copy and paste from first page of TLV320AIC3100 datasheet) -Power Supplies: – Analog: 2.7 V–3.6 V – Digital Core: 1.65 V–1.95 V (DVDD) – Digital I/O: 1.1 V–3.6 V (IOVDD) All digital signals including RESETZ and GPIO follow the voltage range mentioned in DIGITAL INPUT AND OUTPUT section of the Electrical Characteristics table on page 10 of datasheet. There are standard tables in any data sheet with information regarding I2C and I2S and the typical voltage they were measured at (for example VDD=1.8 for this device ) and specs for different IOVDD used. Regards, Arashhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669000/tas2780-tas2780-tdm-sdout-alignment-issue-with-32-bit-tdm8-and-iv-sense-data-transmission/6437958Mon, 03 Aug 2026 18:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fc75538f-b2f7-4a9a-a211-d9ffb304038aIsaac BulivaHi Ben, Speaker voltage sense and speaker current sense sample streams are 16 bit precision, so they will always utilize two TX time slots. Figure 8-3 shows the alignment of time slots with SBCLK and FSYNC: The TDM section under the Advanced Device Control tab of PPC3 can allow full configurability of these slots: Regards, Isaachttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669419/tpa3251-tas3251-vs-tpa3251-dsd1794-for-best-noise-performance/6437952Mon, 03 Aug 2026 18:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4e5364cb-cc8b-49ad-be79-b1e85ae03c4fNicolas BouquetOk, after a quick first read-through, I hadn&#39;t realized that I can bypass the PLL. For a first design, I will start with the TAS, evaluate it and then decide if it&#39;s necessary to complicate the things with an external DAC. Some questions about the PFFB on TAS3251 : - The OUT+ signal is feedback to the IN+, and OUT- =&gt; IN-. I was expecting a negative feedback (OUT+ =&gt; IN-), but I&#39;ve found on the forum that the amp is inverting, so no need to cross the feedback. Am I right ? - Can I directly feedback the OUT signals to IN with the recommended 18k resistor, without using a buffering op-amp between DAC.OUT and SPK.IN ? In this case, maybe the 100k pull down resistor should be removed (this is making a voltage divider) ?https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669578/tlv320aic3105-tlv32oaic3105-with-date-code-a7x3-g4-oscillates-on-power-shutdown/6437937Mon, 03 Aug 2026 17:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bfbc318e-ac47-4c94-b7cf-3c051016eea0Paul SaffrenHi Jeff, We are using two of these devices on our PCB. The board is powered by 12V and contains several DC-DC converters. The board is powered on and off using a power MOSFET (FDS6375). Until we started using this date code we have never seen the &#39;squealing&#39; problem. The TLV320AIC3105&#39;s reset is controlled by a reset monitor device (MCP120T-300) which is designed to generate a reset condition on power transitions. During my tests I have hard wired the reset line low and then removed power, however the oscillation still occurred. So far the problem has occurred on 3 consecutive boards, and in the exact same way. As we continue to turn-up new PCB&#39;s I will have more information as to how many units have this issue. The problem occurs on every power down. Regards, Paulhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669578/tlv320aic3105-tlv32oaic3105-with-date-code-a7x3-g4-oscillates-on-power-shutdown/6437844Mon, 03 Aug 2026 16:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:77771d0b-faf8-4aea-8fc6-1c451a597e40Jeff McPhersonHi Paul, Can you share more information on how you are powering down the device? Is this issue seen on every device you have with this date code, or just some of them? How often does the problem occur? Thank you, Jeff McPhersonhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1668612/am62d-q1-setting-up-rmask-and-rfmt-registers/6437680Mon, 03 Aug 2026 14:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2fc10dd1-1717-4632-94c5-a76775c4bcefshun yaothank u very much!https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669419/tpa3251-tas3251-vs-tpa3251-dsd1794-for-best-noise-performance/6437642Mon, 03 Aug 2026 14:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6e8076cb-9b94-4a30-8341-4eed300fd914Peter Wu5Your concern is legitimate and explicitly acknowledged in the TAS3251 datasheet: &quot;The TAS3251 device is able to meet the specified audio performance while using the internal PLL. However, using the MCLK CMOS oscillator source will have less jitter than the PLL.&quot; Key implications: The internal PLL does​ add phase noise relative to a clean external MCLK The device supports a 3-wire mode​ where SCLK feeds the PLL to generate internal clocks — this is the highest-jitter path For best performance, you should provide a low-jitter MCLK​ (1.024–49.152 MHz depending on sample rate) directly to the MCLK pin, and the DAC section can run directly from MCLK by configuring: Clock Tree Flex Mode (P253-R63 and P253-R64) DAC and OSR Source Clock Register (P0-R14) → set to 0x30 DAC clock divider DDAC (P0-R28) Recommendation for your USB async source: Since your USB async audio block already uses a clean clocking scheme, route that low-jitter clock to MCLK​ and avoid the internal PLL path entirely. This effectively eliminates the PLL phase-noise concern and makes TAS3251&#39;s clock performance comparable to a discrete approach. That said — if your customer is extremely jitter-sensitive (e.g., evaluating pure tones with high-resolution FFT), the discrete DAC approach (DSD1794 → TPA3251)​ does give you more direct control, since the DAC and amplifier clock domains are completely separate and you can optimize each independently.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669419/tpa3251-tas3251-vs-tpa3251-dsd1794-for-best-noise-performance/6437631Mon, 03 Aug 2026 14:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:30da14d3-3c83-47b8-8364-a6e4f6b5ea1dPeter Wu5Hi Nicolas, For the TAS3251, the input is digital​ — there is no analog signal path going directly into the amplifier input stage. The device is a digital-input Class-D amplifier​ with an integrated Burr-Brown DAC and DSP front-end. Therefore, the –60 dB sine signal in Figure 6.12 is applied via the I&#178;S/TDM serial audio port​ (SDIN, BCLK, LRCLK), as a 24-bit digital audio stream representing a –60 dBFS sine wave. The signal flows: I&#178;S digital sine → internal DAC → DSP (optional) → Class-D power stage → LC filter → load This is confirmed by the datasheet&#39;s audio characteristics table, which is measured under the stated conditions (PVDD = 36 V, RL = 4 Ω, fs = 600 kHz) and reports: THD+N at 1 W: 0.008% A-weighted output noise: 95 &#181;V SNR: 108 dB (A-weighted) DNR: 110 dB (A-weighted) So Figure 6.12 reflects the total system noise floor​ of the digital-input path — DAC + DSP + power stage — not an analog sine directly injected. Your concern about &quot;internal DSP and charge-pump generating noise&quot; is valid in principle, but TI&#39;s closed-loop architecture achieves &lt;95 &#181;V A-weighted noise, which is genuinely competitive.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669889/tlv320aic3110-tlv320aic3110---external-filter-circuitsMon, 03 Aug 2026 13:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cd18a216-f1a0-4fcd-ab6a-b7326ace9177Ramakrishna Raja CPart Number: TLV320AIC3110 Hi Team, Do we need to implement any external EMI filter cirucits for HP and speaker if so kindly share reference for them. Kindly help to share a reference for Filter circuitsIndustrial AutomationTLV320AIC3110https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669869/tlv320aic3100-tlv320aic3100---reset-gpio-and-i2s-voltage-groupMon, 03 Aug 2026 12:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f341ce25-a603-4549-998c-114d212c67b9Ramakrishna Raja COther Parts Discussed in Thread: TLV320AIC3100 , TLV320AIC3110 Hi Team, Kindly help to share Reset,GPIO, I2C and I2S Voltage group? like IOVDD/DVDD , where to find these informations? TLV320AIC3110 / TLV320AIC3100Industrial AutomationTLV320AIC3100TLV320AIC3110https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1666745/pcm5100a-clock-rates-and-changing-them-on-the-fly/6437509Mon, 03 Aug 2026 12:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5f80ab9e-ae73-4e90-bbb2-2926c57baf11Garret GodfreyHi Alpesh, I recommend keeping the I2S lines low for power up. Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669746/tac5142evm-k-tac5142evm-k-not-recognized-by-pc/6437497Mon, 03 Aug 2026 12:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a95a054a-71a6-471a-8c45-6c79391487fcArash LoloeeHi Annika, Pleaset try the Attached file e2e.ti.com/.../2018.TI-USB-Driver.zip Regards, Arashhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1666745/pcm5100a-clock-rates-and-changing-them-on-the-fly/6437466Mon, 03 Aug 2026 11:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:013530a5-9596-4c7c-bc90-a90a405211a4alpesh kavia1Hi I got it to work using the following SCK = Fs*512 = 4.194MHz LRCK = 8192Hz BCK = 262,144Hz (x32 mode) I think SCK had to be higher, used to be Fs*128. The lines start-up LOW. SCK starts earlier, 18 SCK clock cycles earlier then LRCK goes HIGH so the right-channel goes out first. Further question; 9) What do you recommend for the start-up/power on for the I2S lines i.e. logic-LOW or logic-HIGH?https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1668612/am62d-q1-setting-up-rmask-and-rfmt-registers/6437365Mon, 03 Aug 2026 09:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d7465941-5e8d-4fd3-961c-8f9bab12edd6Ritapravo SarkerHi Shun, To shift the data up into bits[31:20], set RROT = 12BITS (right-rotate by 12). This maps bit[11] (MSB) to bit[31] and bit[0] (LSB) to bit[20]. RFMT = 0x00018053U; /* RDATDLY=1, RRVRS=MSBFIRST, RSSZ=12BITS, RROT=12BITS — use 0x00008053 for 0-bit (DSP-mode) data delay */ RMASK = 0xFFF00000U; /* keep bits[31:20], zero bits[19:0] */ RFMT field breakdown: RDATDLY[17:16]=01, RRVRS[15]=1, RPAD[14:13]=00, RPBIT[12:8]=0, RSSZ[7:4]=0101 (12BITS), RBUSEL[3]=0, RROT[2:0]=011 (12BITS). After this configuration, each RFIFO word has the 12-bit data in bits[31:20] with MSB at bit[31] and zeros in bits[19:0].https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1664975/tas2320evm-ppc3-not-working-and-no-available-hw-config/6437363Mon, 03 Aug 2026 09:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4f73ab32-e006-4ecd-97f3-9fccd2610d70Peter Wu5Step 2: Perform a &quot;Clean Start&quot; and I2C Recovery To fix the PPC3 connection issue, we need to ensure the TAS2320 chip is responsive. Disconnect Power:​ Unplug the USB cable from the EVM or turn off the power switch. Wait for 5-10 seconds. Reconnect Power:​ Plug the USB cable back in or turn the power back on. Use PPC3&#39;s Console:​ Open the PPC3 software. Navigate to the &quot;System Configuration&quot;​ or &quot;Register Dump&quot;​ section. Look for an &quot;I2C Master&quot;​ or &quot;Console&quot;​ feature. Send a Reset Command:​ Try sending a basic I2C write command to reset the chip. For example, you can try writing to the reset register or the I2C address register. A common first step is to send a &quot;software reset&quot; command. The exact command will depend on your board&#39;s specific configuration, which you should find in the correct version of the User&#39;s Guidehttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1664975/tas2320evm-ppc3-not-working-and-no-available-hw-config/6437360Mon, 03 Aug 2026 09:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:877ecd36-1ede-4c26-9cc9-c5332e3f49e5Peter Wu5Hi Jelle, Please follow these steps in order: Step 1: Consult the Correct Documentation First, stop referring to the outdated manual. Please search for and download the TAS2320EVM User&#39;s Guide ​ that specifically matches the PCB revision printed on your board https://www.ti.com/lit/an/slaaem7/slaaem7.pdf?ts=1785694286757 . You can find the latest documents on the TI website.