https://e2e.ti.com/support/audio-group/audio/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669419/tpa3251-tas3251-vs-tpa3251-dsd1794-for-best-noise-performance/6436684Sat, 01 Aug 2026 01:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:752eea6a-1a58-4af8-b193-cf1befdacd7eShenghao DingOur expert will feedback you next working day.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669578/tlv320aic3105-tlv32oaic3105-with-date-code-a7x3-g4-oscillates-on-power-shutdownFri, 31 Jul 2026 22:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:30f18293-b085-4992-9894-976b1c81846dPaul SaffrenPart Number: TLV320AIC3105 Hello TI Support, We have been using the TLV320AIC3105 CODEC on several of our products for many years. Lately on one product we have noticed what appears to be a difference between devices of different date codes. The problem we are seeing is a rather large audio squeal which starts at a high frequency and then quickly decreases in frequency. The signal is quite loud, when viewed on a scope I measured around 2.0 Vp-p. The issue only occurs on power down, never on power up. Older chips with date codes of CK5P do not exhibit the squeal. I am wondering if TI changed manufacturing processes and this may be the issue? In our design we believe we are correctly bypassing the chip with 10 uF and 0.1 uF capacitors connected between DRVDD and AVDD to ground. Additional 0.1 uF capacitors are connected between DVDD, IOVDD to ground. Thanks in advance for any help. Paultlv320aic3105Wireless Infrastructurehttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669000/tas2780-tas2780-tdm-sdout-alignment-issue-with-32-bit-tdm8-and-iv-sense-data-transmission/6436604Fri, 31 Jul 2026 22:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fb74ce23-81fe-4a4e-8c98-def8edfc4ee9Isaac BulivaHi Ben, Yes, I will provide another update soon, I&#39;m checking this internally to make sure I&#39;m giving the most accurate information. Regards, Isaachttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667905/tlv320dac3100-tlv320dac3100-headphone-idle-noise-rises-after-the-first-audio-playback-and-only-a-hardware-reset-restores-the-quiet-state/6436579Fri, 31 Jul 2026 21:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1f952bfd-9a0a-456a-b0d3-2fe83580ee94Arash LoloeeHi Roberto, Thanks for providing the detail information. I have never seen this phenomena in this device, nor in any other DACs I have worked in the past. I don&#39;t expect the supply voltage of 3.0 is causing this behavior. So I thought the best approach for me is to run the test with the EVM that I have with your script and compare the noise floor. I am using our official EVM along with APX500 to analyze the output . I could not get an output with the above script you sent, so I checked with the script that I had and I did not see any elevated noise before and after sending a 1KHz sinewave. I modified your script and added few lines to its end and got it to work , and further I modified the gain to -34.5dB as it was clipping with 0dB gain setting used. Even with this modified script I did not see any change in the noise level from Idle to 1KHz sinewave case and back to idle case. I think something in your system is causing this and the best approach is to take some of the components out and if possible leave the DAC by itself and rerun the tests to find the culprit. This is a sample script that you can try: e2e.ti.com/.../7041.AIC3111_5F00_Init.txt e2e.ti.com/.../Modfied-script.txt idle noise 1KHz Idle after stopping the 1KHz Hope these can help you with the issue. Regards, Arashhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669225/tlv320aic3256-tlv320aic3256-initialization-and-configuration/6436357Fri, 31 Jul 2026 18:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a9e96467-87c5-43b7-9560-7b6eb17165b0Garret GodfreyHi Alex, Our team is reviewing this request. Thanks and Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669357/purepathstudio-offline-installation-of-ppc3/6436314Fri, 31 Jul 2026 18:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:34037a92-e288-4b17-a255-35fa910675adGarret GodfreyHi Annika, Are you able to install the ppc3.tar.gz file from the Secure Resources download page? Here are some other threads that may assist: https://e2e.ti.com/support/audio-group/audio-internal/f/audio---internal-forum/1362197/purepathconsole-ppc3-sign-in-is-blocked-by-firewall https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1555767/faq-purepathconsole-mcr-persistent-error-in-ppc3?tisearch=e2e-sitesearch&amp;keymatch=mcr# Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669288/opa1692-in-to-v-reverse-bias/6436289Fri, 31 Jul 2026 17:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3a061d3e-92f6-445b-a22c-60a4ea67c0beArt KayToshiro, When checking to see if an input overstress voltage is a problem, you should look at both voltage and current. Also, you need to look directly on the op amp pin. If the input voltage is limited by a resistor so that the current is less than the absolute maximum current, then the part will not be damaged. In your case you have a 2.2k and a 3k input resistor. This will limit the input current to I = (5V - 0.6V)/(2.2k +3k) = 0.85mA. This calculation assumes that the power supply is at zero and the input signal is at 5V (worst case). In your situation, the input signal and supply voltage are actually pretty close together so the current would be much less. The abs max current is &#177;10mA. So, in your case, I don&#39;t think that electrical overstress is a concern. How to Protect Op amps from Electrostatic Discharge &amp; Electrical Overstress Damage covers this topic in detail. Best regards, Arthttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669421/ne5532-year-and-month-of-manufacture/6436253Fri, 31 Jul 2026 17:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8cd55418-13b9-4616-b96d-b64404ac5c87Alex CurtisHello Andreas, The units with this marking (38AGYGM) are from SFAB (legacy material). To help identify which die you have, you can distinguish the legacy die from the new by checking the “CSO” (Chip Source Origin) line of the shipping label and documentation. For the new die, the CSO is &quot;RFB&quot;, which is indicative of the current fab location. Please see the PCN announcing the process change here: PCN #20231114002.1 . Kind Regards, Alex Curtishttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1668740/tlv320dac3100-tlv320dac3100-noise-floor-vs-frequency-additional-details/6436032Fri, 31 Jul 2026 14:18:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:189d49c5-f6a3-45f5-8d4b-7ac691146059Garret GodfreyHi William, I got feedback from our test team that a 96k FFT length and Equiripple window is used to generate the FFT for our newer devices. As I said, this is an older device so it is not certain these conditions were used, but this is our closest estimation. Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1668743/tad5242-noise-floor-vs-frequency-additional-details/6436026Fri, 31 Jul 2026 14:14:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:95f6dd19-b5ba-4794-9cef-bb3dd0d7c6aeGarret GodfreyHi William, I got feedback from our test team that a 96k FFT length and Equiripple window is used to generate this plot. Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667905/tlv320dac3100-tlv320dac3100-headphone-idle-noise-rises-after-the-first-audio-playback-and-only-a-hardware-reset-restores-the-quiet-state/6435964Fri, 31 Jul 2026 12:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3033401e-4484-48d9-981b-09556dd2093dRoberto Cesco FabbroHi Arash, Thanks for your reply, I tried to collect some data and calculation. I hope I haven&#39;t been too verbose! PS A Measurement setup We do not have an audio analyser, so the measurement is made with what is available. It is honest about its own limits and the numbers below are given as lower bounds wherever that applies. Headphones connected — 16 ohm, the normal load, plugged into the jack for every capture. PC sound card, line input, wired in parallel with the headphones at the jack. The load therefore stays the real one; the card only observes it. Capture format: 44.1 kHz, 16 bit signed, stereo. The input gain of the sound card was not touched between the four captures , so the four spectra are directly comparable. Source: ESP32-S3 as I2S master, 48 kHz / 16 bit, DAC as slave, PLL bypassed (CODEC_CLKIN = MCLK = 12.288 MHz). Digital silence on the bus except during the tone capture. Supplies: AVDD = HPVDD = 3.0 V , DVDD = 1.8 V, IOVDD = 3.3 V, each from its own LDO. (Our earlier post quoted 2.8 V for AVDD/HPVDD — that was wrong, the board is fitted with the 3.0 V LDO. See question 4.) How the plots are computed Each plot is a power spectral density , not a raw FFT magnitude: Welch averaging, Hann window, **8192** points, 50% overlap. At 44.1 kHz this gives 5.38 Hz per bin and an equivalent noise bandwidth ENBW = 1.5 &#215; fs/N = 8.08 Hz . Vertical axis in dBFS(A)/Hz : dB relative to full scale, per hertz, with A-weighting per IEC 61672 already applied to the curve. 0 dBFS is a sine of amplitude &#177;32768 LSB, .e. a full-scale sine reads −3.01 dBFS rms. PSD normalisation means the noise pedestal does not move when N changes, so captures taken with different resolutions stay comparable. A tone , on the other hand, reads its level minus 10&#183;log₁₀(ENBW) = −9.07 dB, and that offset is added back when the tone level is quoted. Integrated noise is ∫PSD&#183;df over 20 Hz – 20 kHz , summed in power. Full-scale reference, and why the signal is attenuated by 34.5 dB The SNR needs the device&#39;s full-scale output as the numerator. That signal cannot be recorded directly: at full scale the DAC output exceeds the sound card&#39;s own full scale by about 30 dB , so the input clips. The card&#39;s usable range runs out well before the DAC&#39;s does. So the reference is taken with a known digital attenuation of −34.5 dB (p0 0x41/0x42 = 0xBB) applied to an 800 Hz sine generated at digital full scale, and referred back: measured tone = -14.1 dBFS(A)/Hz + 9.07 dB (ENBW) = -5.0 dBFS(A) full-scale ref = -5.0 + 34.5 = +29.5 dBFS(A) SNR = +29.5 dBFS(A) - integrated noise The digital attenuation does not affect the noise floor. The DAC digital volume control sits upstream of the modulator, so it scales the *signal* only; the analog noise of the output stage is generated downstream and is unchanged by it. This is what makes the method valid — the noise is measured in the real full-gain condition while only the signal is scaled down to fit the card. It is also why we use the digital volume and not the analog volume control (p1 0x24/0x25) for this: the analog one would attenuate signal and noise together and the ratio would be meaningless. Results Attachment Condition Integrated noise Minus setup floor SNR dac_reset.png DAC held in hardware reset −65.3 dBFS(A) this is the setup floor - dac_init.png immediately after init, digital silence −61.5 dBFS(A) −63.9 dBFS(A) 93.4 dB(A) tone.png 800 Hz sine playing, at −34.5 dB digital −49.6 dBFS(A) −49.7 dBFS(A) 79.2 dB(A) after_tone.png` tone stopped, digital silence again −50.2 dBFS(A) −50.3 dBFS(A) 79.8 dB(A) dac_reset.png dac_init.png tone.png after_tone.png The &quot;minus setup floor&quot; column subtracts the reset capture in power, so it is the DAC&#39;s own contribution with the measurement chain removed. All figures are ratios , referred to the device&#39;s own full-scale output. We do not quote the idle noise in &#181;Vrms because we have no calibrated voltage reference for the acquisition chain, and we would rather give you a number we can stand behind than one obtained by extrapolation. The result: After init the device meets the typical spec : 93.4 dB(A), against 95 dB(A) typical in the datasheet. After playing audio it falls to the specified minimum : 79.8 dB(A), against 80 dB(A) minimum. The step is 13.6 dB , and it does not come back. No register is written between the two states — see &#167;6. - `tone.png` and `after_tone.png` agree within 0.6 dB, so the floor is already elevated *while* the tone plays and simply stays there when it stops. The spectral shape is the same in both states: a flat A-weighted plateau from roughly 1 kHz to 8 kHz which dominates the integral, rolling off below 500 Hz and above 10 kHz. The elevated state is that same curve shifted up, not a new mechanism in one band. What it sounds like The instrument agrees with the ear, which is worth stating because it also places the source inside the chip: DAC held in hardware reset: the headphones are silent. Nothing audible at all, as expected — at reset the headphone drivers are powered down (p1 0x1F = 0x00) and the output is muted. Immediately after init, with digital silence on the I2S: the hiss is already audible , though clearly quieter than it becomes later. After the tone has played: the hiss is obviously louder , and it stays that way until the next hardware reset. So the noise appears the moment a register powers up the DAC and the drivers, and it responds to register state. Anything reaching the output from outside the chip — the cabling, the jack, the environment, the board supplies — would not behave that way. The ranking matches the measurement exactly — silent, faint, clearly audible — and the audible step between the second and third case is consistent with the 13.6 dB we measure. Caveats, stated up front: The post-init capture sits only 3.8 dB above the setup floor , so its 93.4 dB(A) carries roughly &#177;2 dB and is a lower bound — the device may be quieter than that. The post-tone capture is 15 dB above the floor and is solid. Discrete lines at 1 kHz and multiples appear in every capture, including the one with the DAC in reset. They are the PC/sound card, not the DAC, and contribute 0.4 dB to the integral. Register configuration Exactly what the firmware writes, in order. `wait` values in milliseconds. # Page 0 — reset, clocks, interface 0x00 0x00 # select page 0 0x01 0x01 # software reset (wait 2 ms) 0x04 0x00 # CODEC_CLKIN = MCLK, PLL bypassed 0x0B 0x81 # NDAC = 1, powered up 0x0C 0x82 # MDAC = 2, powered up 0x0D 0x00 # DOSR MSB 0x0E 0x80 # DOSR LSB = 128 (NDAC*MDAC*DOSR = 256) 0x1B 0x00 # I2S, 16 bit, DAC is slave 0x3C 0x01 # processing block PRB_P1 # Page 1 — analog routing and headphone drivers 0x00 0x01 # select page 1 0x1F 0x04 # common mode 1.35 V, HP drivers still off 0x21 0x4E # de-pop: driver power-on 1.22 s, ramp step 3.9 ms 0x23 0x44 # LDAC -&gt; HPL, RDAC -&gt; HPR (AIN1/AIN2 not routed) 0x28 0x06 # HPL driver: PGA 0 dB, not muted 0x29 0x06 # HPR driver: PGA 0 dB, not muted 0x1F 0xC6 # power up HPL + HPR (wait 1300 ms, covers the de-pop ramp) 0x24 0x80 # HPL analog volume: 0 dB, routed to driver 0x25 0x80 # HPR analog volume: 0 dB, routed to driver # Page 0 — DAC power-up and unmute 0x00 0x00 # select page 0 0x43 0x00 # headset detection disabled 0x74 0x00 # VOL/MICDET SAR ADC off, volume from registers 0x3F 0xD4 # power up DAC L and R, soft-stepping enabled 0x41 0x00 # DAC left digital volume = 0 dB 0x42 0x00 # DAC right digital volume = 0 dB 0x40 0x00 # unmute DAC L and R (wait 50 ms) State during the measurements All three gain stages at unity, which is the condition the datasheet SNR is specified in: Stage Register Value Gain DAC digital volume p0 0x41 / 0x42 0x00 0 dB Analog volume (HP) p1 0x24 / 0x25 0x80 0 dB, routed to driver HP driver PGA p1 0x28 / 0x29 0x06 0 dB, unmuted DAC mute p0 0x40 0x00 not muted The only deviation from this, and only for `tone.png` , is the digital volume set to 0xBB (−34.5 dB) as described in &#167;3. For `dac_init.png` and `after_tone.png` the digital volume is 0x00 (0 dB) and the I2S carries exact digital zero. What changes between &quot;before the tone&quot; and &quot;after the tone&quot; Nothing that we write . Specifically: the tone command writes no DAC register at all — it only pushes I2S samples. Between `dac_init.png` and `after_tone.png` the host performs zero I2C transactions; the I2S clocks (MCLK, BCLK, WCLK) run continuously in both states — they are never stopped; the I2S data is exact digital zero in both states. The DMA descriptors are zero-cleared after transmission, so the bus returns to all-zero samples the moment the tone ends (verified in the driver, and audible as the tone stopping cleanly with no residual); no reset, no mute/unmute, no power-down between the two captures. The only difference between the two states is the history : whether the device has processed non-zero samples since the last hardware reset. A further hardware reset plus re-init restores the quiet state. Verified by reading the device, not only asserted from the host side. We read back all 128 registers of page 0 and all 128 of page 1 immediately after init, and again after the tone had stopped, and compared the two states register by register: all 256 values are identical — not a single bit changed. Identical in both states, among others: digital volume p0 0x41/0x42 = 0xBB (the −34.5 dB of &#167;3, set *before* the first read-back, so the tone is the only event between the two), DAC powered up and unmuted (p0 0x3F = 0xD4, p0 0x40 = 0x00), headphone drivers powered with the analog volume at 0 dB and routed (p1 0x1F = 0xC6, p1 0x24/0x25 = 0x80). So between a measured 93.4 dB(A) and a measured 79.8 dB(A) there is no register difference of any kind, on either page. We can send the two full dumps if that is useful. Questions 1. Is this behaviour expected? Is the post-audio floor the specified one, and the post-init floor simply a degenerate idle state of the modulator with an exactly-zero input — or is the reverse true, and something in our sequence is leaving the device in a noisier state once excited? 2. Is there a way to return to the quiet state without a hardware reset? For example a recommended DAC power-down/power-up (p0 0x3F) or mute/unmute sequence, or a processing block that behaves differently here? 3. Does the choice of processing block (p0 0x3C = PRB_P1) or the soft-stepping setting (p0 0x3F D2:D1) influence the idle noise floor in either state? 4. AVDD/HPVDD at 3.0 V. Recommended operating conditions are 2.7 V min / 3.3 V typ / 3.6 V max, and the Electrical Characteristics are specified at 3.3 V. This board supplies 3.0 V to both. How much idle-channel noise degradation should we expect from running 0.3 V below the characterisation point, and could it explain the elevated state sitting at the 80 dB(A) minimum? We can repeat the measurement at 3.3 V from a bench supply if it helps. Thank you very much Robertohttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667034/tas5805m-tas5805m-unable-to-output-audio/6435850Fri, 31 Jul 2026 10:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f5351dda-79fc-4e20-b1f8-a052a3ed6916Gu ZhouIs there a problem with my audio? I converted it from a WAV file. Do you have any test audio sources?https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667034/tas5805m-tas5805m-unable-to-output-audio/6435847Fri, 31 Jul 2026 10:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:99779f8b-13f5-420e-9fca-9467690879c5Gu ZhouHi Wenbin Li, I used the initialization sequence generated by PPC3, but it still sounds like a long beep. I read back the status of the register reg28=0x0 reg33 = 0x2、reg34 = 0x0、reg37 = 0x9、reg38 = 0x20、reg39 = 0x8、reg68 = 0x3、reg70 71 72 73 = 0https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667013/tpa2005d1-q1-tpa2005d1-q1-overheating-issue-in-enabled-state/6435809Fri, 31 Jul 2026 09:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1bcc4334-14ff-4a68-896f-83e81e99b0b7Ann Sara BabyHi Wang, The speaker impedance we are using is 8 Ω . Since the PCB footprint is 0603 , I found that the recommended 0.6 A inductors are available only in much larger package sizes. However, I noticed in the datasheet that if the trace length is less than 100 mm , an RC filter circuit is not required . Could you please confirm whether it is acceptable to remove the RC filter circuit and test the board without it to see if the heating issue still persists? Regards, Annhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669421/ne5532-year-and-month-of-manufactureFri, 31 Jul 2026 09:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cbf3ca5e-fab8-44ac-ae34-ccce45ae6217Andreas UhlfelderPart Number: NE5532 Dear Ladies and Gentlemen, Could you please tell me when this IC was manufactured and which specifications apply to this component? There were changes regarding the supply voltage starting in 2025. NE5532P Code 38AGYGM With best Regards from Germany A.UhlfelderNE5532https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1669419/tpa3251-tas3251-vs-tpa3251-dsd1794-for-best-noise-performanceFri, 31 Jul 2026 09:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fec2fa5f-d39f-4953-9cd8-06f7e6c81f05Nicolas BouquetPart Number: TPA3251 Other Parts Discussed in Thread: TAS3251 , , NE5534 Hello, I have a device streaming 24 bits audio data from an USB source (async mode, USB audio class 2). The amp will be around 100W power, it must be as good as possible (THD+N) at low volume (1~10W). I am thinking about 2 differents schemes : USB audio =&gt; I2S =&gt; TAS3251 USB audio =&gt; I2S =&gt;DSD1794 =&gt; op-amp I/V conversion =&gt; TPA3251 One one side, the TAS integrate all needed parts, making the hw design extremly simple. But the internal DSP and charge-pump may generate some noise, degradating the noise performace and dynamics when output voltage is low. The DSD1794 DAC is offering incredible THD, noise and dynamics. Coupled to the TAP device, I think it could perform better, but hardware is much complicated. Some questions : 1- To obtain the figure 6.12 of the TAS3251 datasheet (noise vs frequ @ -60dB input), how is applied the sine input ? Using the I2S input or applying a sine directly on the amp input ? 2- My customer is also questionning about phase noise. Some phase noise on a PLL or clock source may introduce jitter on the samples. The audible result is that a pure tone (like a piano key), instead of producing a clean frequency peak, will spread out around the central frequency. My USB async audio block is using a very clean clocking scheme to avoid this artifact. The TAS has an internal PLL that may add some phase noise on the samples. This point is not so easy to characterize and anticipate. I would be more confient to start with the TPA. 3- What would be the recommended op-amp circuitry between DSD DAC and TPA ? The datasheet gives some schematics with NE5534 and LT1028, but it&#39;s 20 years old, we can probably use better op-amps now. The TPA datasheet indicates &quot;Vin - Maximum input voltage swing = 7V&quot;, does that meas the signal should be in 0-7Vpk (2.47Vrms) ? The DSD output is -6.2 +/-3.9mA. This is a 7.8mApp variation that should become 7V, meaning the R value of the I/V converter should be 7V / 7.8mA = 897ohm =&gt; The nearest standard, 866 ohm, would be the best choice to optimize the dynamic range without saturating the input. Then, the signal must be AC-coupled. How is calculated C ? This is simply a RC filter, does R is the internal 24kohm resistance ? Is this internal R-value stable enough ? Thanks for your advices, RegardsTPA3251TAS3251NE5534https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667645/tas67524-q1-comparison-with-the-tas6424e-q1/6435779Fri, 31 Jul 2026 09:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:68502d14-77e3-49d6-b279-52e5caa87c83Shadow HeHi Gemma-san [quote userid=&quot;461440&quot; url=&quot;~/support/audio-group/audio/f/audio-forum/1667645/tas67524-q1-comparison-with-the-tas6424e-q1/6435482&quot;]What would be the recommended value for the TAS6424E-Q1?[/quote] TAS6424E doesn&#39;t have this limitation, no problem to use any 2ohm speaker.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667034/tas5805m-tas5805m-unable-to-output-audio/6435769Fri, 31 Jul 2026 09:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ad3da857-1749-4390-a1c1-b23f144db593Gu ZhouHi Wenbin Li, Yes, I also thought of it. I just switched to a personal network and downloaded it successfully. Thank you.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667034/tas5805m-tas5805m-unable-to-output-audio/6435767Fri, 31 Jul 2026 09:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:511a10d3-cfc6-4055-bb38-c192a77eb35fWenbin Li1Hi Gu Zhou, usually the company network may have some limitations. you can try personal or home networks. Br, Wenbinhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1667034/tas5805m-tas5805m-unable-to-output-audio/6435751Fri, 31 Jul 2026 08:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9e388b8a-b71c-436f-aa0e-06c92bb1bac3Gu ZhouContinuously failed to download, failing every time it reaches 30%, with the prompt &#39;Problems occurred during installation of TAS5805M. Refresh Available EVM Apps before trying again&#39;