https://e2e.ti.com/support/audio-group/audio/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693163/tas2505-q1-tas2505-q1-corner-footprint-padsTue, 27 Oct 2026 21:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ea10c062-9c04-46bc-b32e-bd7671cf89a8Mark OmoPart Number: TAS2505-Q1 The TAS2505-Q1 Datasheet has 4 extra pads on the footprint A1-4 at the corners. Are thease required? What is their function? What should be done with the lands? Floating? Ground?TAS2505-Q1https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693132/tlv320adc3120-2-channel-summing/6522858Tue, 27 Oct 2026 19:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bc93d77a-8054-4868-93e1-f75971717fa0Desmond KekHello Garret, thanks for clarifying. Could you also please help me verify that this section is correct?https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693132/tlv320adc3120-2-channel-summing/6522785Tue, 27 Oct 2026 18:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:967a82ce-dac2-4d8c-9045-2282e6734acfGarret GodfreyHello, You should short the INPs together and the INMs together. I believe the document has a typo. Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693126/tas5827-the-audio-technology-issue/6522769Tue, 27 Oct 2026 18:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1f6bd014-58c4-45ab-bef6-4806f66e8015Isaac BulivaHi Zhang, The I2C register map for TAS5827 is available here for your reference: https://www.ti.com/lit/ds/symlink/tas5827.pdf#page=46 Regards, Isaachttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693108/tas5805m-tas5805m-converting-speaker-outputs-to-stereo-line-level-click-and-hiss-during-playback-transitions/6522759Tue, 27 Oct 2026 18:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f650edb0-ab21-47d8-9c85-d87b0e80dd1cIsaac BulivaHi Robert, 1. TI documentation doesn&#39;t contain a validated differential Class-D to ground-referenced line-level reference design. In BD modulation mode, Class-D audio amplifiers produce a common-mode voltage of PVDD/2 after the L-C filter at idle status, which is the average value of the 50% duty-cycle PWM switching waveform in the BTL rather than being ground-referenced . 2. The Type-2 LC filter ( https://www.ti.com/lit/pdf/SLAA701 ) is a common-mode filter primarily used for BD modulation and will need to have a cutoff below the PWM switching frequency. 3. Yes, an audible artifact such as the pop noise is possible at PWM start and stop. The pop noise effectively quantified as an output peak voltage that gets played across the speaker before settling of the amplifier output, during power-up and power-down of the amplifier. The pop noise is an audible artifact on the speaker that usually appears during power-up and shutdown of the speaker driver, but can also occur during idle channel condition when audio amplifier receives no input and isn’t playing any audio. During start of the PWM from shutdown state (or stop), the differential error pulses start to build at Class-D output from zero error voltage hence resulting in a spectral energy that leaks into audio band. This can be caused by amplifier output differential offset. 4. Yes a speaker load is typically used. It&#39;s not strictly required to produce output, but the device architecture assumes a differential, filtered load. 5. Pop is usually mitigated through firmware changes. For external circuitry considerations, an output inductance that is too small may lead to a larger ripple causing the OUTP and OUTN to be unbalanced triggering a pop during power-up. Mismatch LC filters can also cause the offset into the speaker to be different on both legs causing the pop. Sensitive speakers will move in and out very easily. When a speaker moves, there is always some back EMF that can be seen. If a speaker is super sensitive, this can occur even at super small levels, so any small offset can cause this to occur. A snubber on the speaker output can also be used ( https://www.ti.com/lit/an/sloa201/sloa201.pdf ). 6. Check out this app note which details how pop noise is measured: https://www.ti.com/lit/pdf/SLAAED0 . Regards, Isaachttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693132/tlv320adc3120-2-channel-summingTue, 27 Oct 2026 18:08:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:be9f7d51-396a-4d19-881e-a979a5ba0bccDesmond KekPart Number: TLV320ADC3120 Hello, I would like to use the channel summing feature on TLV320ADC3120. In this document , it says to connect the input signal to IN1P and IN2M whilst shorting IN1M and IN2P to ground. But in another forum post I saw that you recommended connecting the input signal to IN1P and IN2P and shorting IN1M and IN2M to ground. Could you please confirm which is correct?TLV320ADC3120Connected peripherals &amp; printershttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693126/tas5827-the-audio-technology-issueTue, 27 Oct 2026 17:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:27b7ff55-1595-496f-aa32-b5b2eacb3277Zhang LiangPart Number: TAS5827 Hi, The current project uses the BTL mode with TAS5827, do you have any reference for I2C register? I don&#39;t understand what the code is doing. Currently, the PWM signal from the amplifier backend still isn&#39;t coming out, the sound can be heard through the hardware method. The below is the data: IIC_001.txtIndustrial AutomationTAS5827https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693021/tad5242-tad5242-elevated-noise-floor/6522704Tue, 27 Oct 2026 17:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b5185c50-3689-4e73-bb75-4d1e8bead09bGarret GodfreyHi Frederik, Can you share a waveform image of the clocks sent to the TAD5242? What are the measured VREF and DREG voltages? Do you have any TAD5242 from a different lot to perform an A-B-A swap? Thanks and Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692101/tad5242-tad5242-power-up-power-down-sequence-din-state-before-power-up-and-bclk-high-state-during-power-down/6522693Tue, 27 Oct 2026 17:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ddf42659-503b-4301-b6c6-7955c92a210cGarret GodfreyHi Kyohei-san, Can you share the MD pin settings? Is the BCLK an input, and the controller MCU pulls the BCLK low the same way in both cases? Are you suggesting the TAD5242 is pulling BCLK high during power-down, even when the MCU drives it low? It would be nice to see an image of this power-down and the two cases. Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692665/tlv320adc6140-maximum-injection-current/6522688Tue, 27 Oct 2026 17:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bb6ad40c-e919-497e-b458-19fc84644913Garret GodfreyHi Luigi, The circuit I posted includes a 100ohm resistor, diode clamp to AVDD and GND, and 1uF DC-blocking cap, no 1kOhm resistor. Either way, I have no guarantee that this particular circuit will protect against 48V transients, and also it is primarily meant for protection during active operation when AVDD is powered. My primary guidance is that when AVDD=0V, proper precaution should be taken such that no voltage reaches the input pin, or at worst less than 0.3V. There are no methods of user-controlled analog gain adjustments during normal operation. Changing the channel gain while the ADC is active can lead to audible artifacts, and the new gain setting will likely not be set as programmed. Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693108/tas5805m-tas5805m-converting-speaker-outputs-to-stereo-line-level-click-and-hiss-during-playback-transitionsTue, 27 Oct 2026 16:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b0e440b2-a9f2-4e02-87f4-0b18ef08750fR NappoPart Number: TAS5805M Hello TI Audio Support, I’m modifying an Amazon Echo Show 15 to provide wired stereo line-level audio to an external amplifier. We previously identified its amplifier from board markings as the TAS5805M. I can provide a board photo for verification. The speaker outputs currently feed a passive Kicker 46KISLOC speaker-to-line-level converter. I hear a click at the beginning of an Alexa response, low-level hiss during speech, and another click when the response or music ends. These symptoms are audible directly at the converter output, before the downstream cabling and amplifier. A separate continuous hum was eliminated by connecting the converter’s ground wire to the Show’s chassis, but the click and hiss when the show responds remain—even at the converter’s lowest gain setting. Could you help clarify: What circuit or reference design do you recommend for converting the TAS5805M’s differential Class-D outputs to ground-referenced stereo line level? What filtering is needed to reject switching content and common-mode voltage? Could these symptoms relate to transitions between idle and playback, or to how the converter loads the outputs? Is an external speaker load required when using the outputs this way? Can this be addressed with external circuitry without changing the Echo’s firmware or amplifier registers? What measurements would distinguish source noise from converter/interface noise? My goal is clean, full-range stereo audio for music and short Alexa responses, without clicks, hiss, or loss of the beginning of speech. I would appreciate guidance on the correct interface before purchasing or building a replacement. Thank you, RobertTAS5805MHome theater &amp; entertainmenthttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692995/tlv320aic3104-output-channel-flc-issue/6522633Tue, 27 Oct 2026 16:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:06b732fd-2617-427c-b772-cebb12c0e55bGarret GodfreyHi Falguni, Can you clarify what you mean by FLC? Can you provide a schematic? Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692662/tlv320aic3104-grounding-strategy-for-audio-driver-pcb/6522580Tue, 27 Oct 2026 15:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:083f73d5-046b-466d-8b8f-2527c9de9ba8Garret GodfreyHi Falguni, PGA2311 is owned by a different team so I am unable to confidently comment. Please kindly create a new thread with PGA2311 as the selected device. Thanks and Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692830/tas5431-q1-standby-quit-time/6522316Tue, 27 Oct 2026 12:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d14714bb-d05a-4f10-9234-e5f7ff1e0d08Dylan YaoRyan, Standby Exit Time: ~229 ms (nominal) The TAS5431-Q1 begins waking and running load diagnostics immediately when STANDBY is deasserted (driven high) 1 . Audio output starts only after that diagnostic sequence completes. Case Time to audio No fault (nominal) ~229 ms — four-phase diagnostic sequence 1 Fault detected or large output capacitance ~429 ms — check phase repeats up to five times 1 Persistent short (load, supply, or ground) Indefinite — diagnostics repeat until the fault clears 1 Dylanhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1693021/tad5242-tad5242-elevated-noise-floorTue, 27 Oct 2026 12:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2280cb6c-dbb8-4ae3-8980-59c718c8a91bFrederik Br&#252;cknerPart Number: TAD5242 Other Parts Discussed in Thread: PCM5242 , TAA5242 We are currently vetting TAD5242 if it fits our application. Pre-requisite: Test board with two TAD5242 daisy-chained together. Layout follows the datasheet implementation guidelines. 4-Layer board, solid ground planes on the inner layers, clocks are routed as far away from analog part as possible, decoupling capacitors as close to the TADs as possible and everything tied to GND with shortest return path. All capacitors on the power rails X7R or better. Config: MD0 4k7 to GND -&gt; Target TDM Mode MD1 HIGH MD2 HIGH -&gt; AVDD=3.3V, Word Length=32, Low-latency phase Filter MD3 LOW MD4 LOW MD5 LOW -&gt; Differential Output, Line-Out only MD6 -&gt; DIN of second TAD fS = 48 kHz BCK = 128 * FS 4 Channel Audio output working fine. However: In powered up mode, but no clocks supplied, noise floor is at around -140dBu with very flat spectrum (measurement setup inherent noise floor R&amp;S UPD). As soon as clocks arrive and TAD activates the internal audio engine, the noise floor rises to -90dBu. (DIN tied to GND or supply digital zeroes, does not make any difference). Noise spectrum is flat, no clock peaks or other other artifacts visible. With max. output of 2 VRMS = 8.239 dBu my expectation of digital zero noise floor is to be a minimum of -111.761 dBu to match the claimed 120dB dynamic range. Right now we are at least 20dB off target and I do not understand where it all goes wrong. Already tried: Supply differnt clocks -&gt; no change. Use very clean lab supply for 3.3 V supply -&gt; no change. Use additional filtering between IOVDD and AVDD -&gt; no change. Use bigger capacitors on VREF pin, optimize GND routing,.. -&gt; no change. I was expecting to see at least some discernible differences with at least some of the modifications, but there is virtually zero change in behavior. For this test setup we removed the op-amp stage on the output completely and measure TAD5242 output directly, to find the source of noise in the system. From everything we have seen, this must come from the TADs internally, since nothing we tried externally, changed the noise floor in any way. Silicon marking: TAD5242 TI578 A26R PCM5242 on an identical test board behaves very well and there is no elevated noise floor. TAA5242 also behaves pretty much as expected. Somehow TAD5242 is giving us a hard time or expectations don&#39;t match. Please advise.TAA5242PCM5242TAD5242https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692995/tlv320aic3104-output-channel-flc-issueTue, 27 Oct 2026 10:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e8e13457-2566-44bd-95be-2af966c25b18Falguni SharmaPart Number: TLV320AIC3104 We are currently using the TLV320AIC3104 for our application. We want three independent volume controllable outputs, so we want to use FLC as an independent output. The problem we are currently facing is that when I connect FLC to the onboard RC filter, it does not stay at the ground reference and instead drifts to a 1.3 V offset. However, when I connect a 100 kOhm resistor from FLC to ground, it stays at the ground reference. What we want to know is the best resistor value or solution to keep FLC at the ground reference without any stability or offset drift issues. Regards, Falguni SharmaMedical &amp; healthcareTLV320AIC3104https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692662/tlv320aic3104-grounding-strategy-for-audio-driver-pcb/6522144Tue, 27 Oct 2026 09:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0a177ea3-ded0-48ad-adcf-06c4e66dfd8eFalguni SharmaThank you for the clarification. In my PCB, I am also using two PGA2311 ICs, along with three OPA1612s, three TPA6120A2s, a TLV320AIC3104 codec, and a level shifter. The PGA2311 datasheet recommends separate analog and digital ground planes connected at a single point. However, I would prefer to use a single continuous solid ground plane for the entire PCB. Can I use a single solid ground plane for the PGA2311 as well, with proper component placement and return-current routing, or should I strictly follow the separate AGND/DGND plane recommendation? Would using a single ground plane affect the PGA2311&#39;s noise performance or cause crosstalk in this audio driver circuit? Thank you!https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692101/tad5242-tad5242-power-up-power-down-sequence-din-state-before-power-up-and-bclk-high-state-during-power-down/6522131Tue, 27 Oct 2026 08:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:908a4c1b-294c-49b4-9219-473f2242abacKyoheiHi Garrret-san, Thank you for your support. We shared your feedback with our customer, and we received an additional question regarding item 3. The customer understands that BCLK should be Low at least 10 ms before the supplies are powered down. However, according to the customer&#39;s evaluation, the behavior is as follows: When the TAD5242 is connected, BCLK remains High for approximately 1 second during the power-down sequence. When the TAD5242 is disconnected and the BCLK signal is measured independently, this approximately 1-second High condition does not occur, and the required power-down sequence can be satisfied. Therefore, the customer believes that this behavior is related to the connection with the TAD5242. Could you please advise how the customer should handle this condition in order to satisfy the TAD5242 power-down requirement? In particular, could you please advise whether any external circuit modification or other recommended measure is required to ensure that BCLK is Low at least 10 ms before powering down the supplies? If necessary for further investigation, we can provide the waveforms measured during the customer&#39;s evaluation via private message. Best regards, Kyoheihttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1692665/tlv320adc6140-maximum-injection-current/6522126Tue, 27 Oct 2026 08:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9f7593fb-072e-4ce6-8faf-d9ea6b4eb9dfLuigi OssimprandiHi, and sorry for my insisting Thank you very much for your detailed response and the suggested protection circuit. This is exactly the kind of technical information we needed. I have two additional questions regarding our design. 1. Input protection – 470 Ω vs. 1 kΩ We intend to use your suggested protection topology, with a 100 Ω resistor before the external Schottky clamp diodes and a series resistor between the clamps and the ADC input. For our microphone inputs, we would like to minimize signal attenuation and thermal noise, especially when using the ADC&#39;s 2.5 kΩ input impedance setting. Would reducing the suggested 1 kΩ resistor to 470 Ω still provide adequate protection against +48 V phantom-power switching and hot-plugging transients? Is the 1 kΩ value based on a specific worst-case condition or simply a conservative recommendation? We also have a separate 100 kΩ series PAD for LINE operation, which is bypassed in MIC mode. 2. Changing analog gain during operation The TLV320ADC6140 datasheet recommends configuring the channel gain before enabling the ADC channel and not changing it while the channel is active. Is this restriction primarily intended to prevent audible artifacts (clicks, pops or temporary distortion), or are there other technical reasons? If we change the channel gain register while the ADC is operating, would the new gain normally take effect without restarting the channel? Since the device already supports dynamic analog gain adjustments through the DRE, is there a recommended method for implementing user-controlled analog gain changes during normal operation without interrupting the audio stream? We understand that digital volume can be adjusted dynamically, but we would prefer to preserve the best possible signal-to-noise ratio by using analog gain whenever appropriate. Thank you again for your help. Best regards, Luigi Ossimprandihttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1688263/tas2563-high-frequency-noise-during-mute-digital-volume-at-0/6522024Tue, 27 Oct 2026 06:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f32de2ed-ff39-4916-822e-511edad0feb5Wenbin Li1Hi Yu Sato, as there is no response for long time, I will close this thread. if you still have issue on this, you can reopen it or create a new one. Br, Wenbin