https://e2e.ti.com/support/audio-group/audio/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1649832/tlv320aic3104-the-gpio-voltage-issue/6360873Wed, 27 May 2026 15:14:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cbece5fe-f0ad-44ff-b957-4ca0695d1d86Garret GodfreyHi Zhang, This looks like TLV320ADC3140, not TLV320AIC3104. Anyway, GPIO operates at the IOVDD voltage level. Since IOVDD is 1.8V, GPIO supports 1.8V. Best, Garrethttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1640304/tlv320aic3204evm-k-could-not-do-flashing-after-flash-i-did-not-run-remove_minievm-file-so-flash-is-not-done/6360676Wed, 27 May 2026 13:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1d509f9e-f703-4681-ab34-308bdc38b145SHARON PSHi , Currently i am try to get audio from our default comdition so I am use BCLK =3mhz LRCK = 48khz MCLK =12mhz but i did not get AUdioi data from devuce why ?? I will share my current configuration here , //test 12mhz 48khz const codec_register CODEC_DEF_REG_DATA [] = { // ---- Page 0: Reset + Clock ---- { 0 , 0x00 }, // Select Page 0 { 1 , 0x01 }, // Software reset (wait 1ms after) { 0 , 0x00 }, // Select Page 0 { 4 , 0x03 }, // PLL_CLKIN = MCLK, CODEC_CLKIN = PLL { 5 , 0x91 }, // PLL power up, P=1, R=1 { 6 , 0x07 }, // J=7 { 7 , 0x00 }, // D MSB { 8 , 0x90 }, // D LSB (D=0.144 → Fout=12MHz&#215;7.144/2/2 = ~48kHz path) { 27 , 0x0C }, // I2S, 16-bit, codec slave { 11 , 0x82 }, // NDAC=2, powered up { 12 , 0x87 }, // MDAC=7, powered up { 13 , 0x00 }, // DOSR MSB { 14 , 0x80 }, // DOSR=128 { 18 , 0x82 }, // NADC=2, powered up { 19 , 0x87 }, // MADC=7, powered up { 20 , 0x80 }, // AOSR=128 { 29 , 0x01 }, // BDIV_CLKIN = DAC_CLK { 30 , 0x82 }, // BCLK N=2, powered up // DAC &amp; ADC processing blocks { 60 , 0x08 }, // DAC PRB_P8 { 61 , 0x01 }, // ADC PRB_R1 // ---- Page 1: Analog power + MIC routing ---- { 0 , 0x01 }, // Select Page 1 { 1 , 0x08 }, // Disable weak AVDD { 2 , 0x00 }, // Enable Master Analog Power Control { 10 , 0x00 }, // Common mode = 0.9V { 71 , 0x32 }, // MicPGA startup delay = 3.1ms { 123 , 0x01 }, // REF charging time = 40ms { 51 , 0x68 }, // MICBIAS: powered up (D6=1), 2.5V (D5-D4=10), from AVDD // Route IN3L → LEFT_P at 20kΩ (D3-D2 = 10 = 0x08) { 52 , 0x08 }, // IN3L to Left MICPGA P-terminal, 20kΩ // Route CM → LEFT_M at 20kΩ via CM1L (D7-D6 = 10 = 0x80) { 54 , 0x80 }, { 59 , 0x77 }, // Left MICPGA: unmuted (D7=0), gain=6dB (0dB channel gain with 20kΩ) { 60 , 0x80 }, // Right MICPGA: muted // ---- Page 0: Power up ADC ---- { 0 , 0x00 }, // Select Page 0 { 81 , 0xC0 }, // Power up Left + Right ADC { 82 , 0x00 }, // Unmute ADC { 83 , 0x28 }, // Left ADC digital volume +12.5dB { 84 , 0x1B }, // Right ADC digital volume +13.5dB }; Currently I am trying to get audio data using the EVM default condition. My setup is: MCLK = 12 MHz BCLK = 3 MHz LRCK = 48 kHz I am using MCLK, BCLK, and LRCK generated from the EVM and connecting them to the nRF54L15 board. However, I am not receiving any audio data on the nRF54L15 side. One issue is that ADC data remains zero. I am trying to use the IN3L microphone input, but I do not get any ADC values from the EVM. My codec ADC initialization completes successfully, clocks are present, but ADC samples remain zero. Could anyone help identify possible issues? I would like to know whether the problem is related to IN3L input routing, microphone path configuration, I2S clocking, or Nordic I2S reception configuration. Thank you.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1649832/tlv320aic3104-the-gpio-voltage-issueWed, 27 May 2026 11:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:92600dae-78cd-4c7b-9680-02b349cb3f75Zhang LiangPart Number: TLV320AIC3104 Other Parts Discussed in Thread: TLV320ADC3140 Hi, We design TLV320AIC3104 for the Audio project, and the platform is Qualcomm CQ7790C SOC, We use TLV320AIC3104 GPI/O to connect with DMIC but the DMIC is 1.8V VCC, and CQ7790 IO voltage is also 1.8V, So we want to know if the GPI/O is support 1.8V voltage or not, if we need to add the level shifting IC in this design? The below is our schematic diagram for your evaluate, thanks.TLV320ADC3140Industrial AutomationTLV320AIC3104https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1647080/tas2505-low-audio-output-with-tas20505-digital-input-speaker-amplifier/6360467Wed, 27 May 2026 10:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d0571dc6-03a2-4f68-b6ed-fe14a9e64565Shenghao DingIn Linux, you can set it with i2cset, which is the standard tool for i2c device in Linux. you can also hardcode it in the driver.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1647080/tas2505-low-audio-output-with-tas20505-digital-input-speaker-amplifier/6360193Wed, 27 May 2026 06:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:38cf4c53-651d-4dc6-91af-d26a3a10879aSubramanian GurusamyFor setting this D7~D6, in page 0, register 27. is there any tool we can use, kindly sharehttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1649467/am62d-q1-capture-not-working-with-12-00-00-07-04-linux-sdk/6360103Wed, 27 May 2026 06:09:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:301f9337-222d-4d86-bb43-b03fb2fe5471Divyansh MittalHi Somnath, Allow me sometime to look into this and get back to you by end of this week.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1640304/tlv320aic3204evm-k-could-not-do-flashing-after-flash-i-did-not-run-remove_minievm-file-so-flash-is-not-done/6359966Wed, 27 May 2026 04:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:51dedc1b-4392-4251-9d2d-634c494e19adSHARON PSGarret Godfreyhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1645862/tlv320aic3107-output-level-higher-than-agc-target-gain-setting/6359957Wed, 27 May 2026 04:10:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ecbc4732-7a3b-4ec8-a30a-2d1724b2d48auser1238011Hi, I also performed a sweep test. However, please note that the target gain setting in my test differs from the condition discussed in my original question. Also, due to measurement equipment limitations, both the input and output measurements are analog signals. In your test, AGC disengagement was observed at low signal levels. I could not confirm that behavior on my side. However, I believe the reason is simply that my measurement equipment cannot generate sufficiently low input levels. In my measurements, the AGC remained active over the entire input range, and the output level stayed nearly constant. Also, this output level is higher than the configured target gain, which is the issue I am investigating. I believe your measurement results and mine are consistent in many aspects. 1.In your measurements, the transition from approximately -45dBrG to -2dBFS appears to indicate that the AGC became active. There may be discussion regarding the input level at which AGC becomes active, but I do not believe that point is strongly related to the main issue. 2.In your measurements, from approximately -43dBFS input up to 0dBFS input, although there are some partial level reductions, the output remains approximately constant at -2dBFS, which suggests that AGC is operating. Also, since this is approximately +6dB higher than the target setting of -10dBFS, I believe this behavior matches the phenomenon I am observing. There are also some differences between our measurements. 1.In your measurements, the level drops toward approximately -10dBFS around -25dBrG, but I could not observe this behavior in my measurements. One possible reason may be that our measurement points are different. You mentioned that you are measuring the ADC output, so I assume you are observing the digital data after AGC processing. In my case, I am measuring the analog signal after the digital data passes through the DAC. This difference may be one contributing factor. 2.In my measurements, the level begins to decrease once the input exceeds approximately 450mVrms. When I checked this using an oscilloscope, waveform distortion was visible and the peak voltage was reduced. Therefore, I believe the level reduction is caused by waveform distortion. In your measurements, I assume that 0dBrG corresponds to the target gain, so input levels above the target gain may not have been tested. One concern I have is regarding your measurement point. Since this is fundamentally the behavior of the IC itself, I believe it would be better to evaluate both the input and output using analog signals. Also, I believe it would be useful to test input levels higher than the target gain. My understanding is that AGC is intended to maintain a nearly constant output level over a wide range of input levels, from below the target level to above the target level. Therefore, if the input signal exceeds the target level, the AGC should apply negative gain adjustment in order to maintain a constant output level. Kind regardshttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1644806/tas5830-ppc3-pure-path-console-install-sw/6359868Wed, 27 May 2026 02:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:806a21ff-407c-4e27-b047-90c15ff210ddWenbin Li1Hi Han, the approval account is &quot;dh.kim2@picode.co.kr &quot;. and some time it will take 1 working day to be effective. please check again later today. I will follow this internally. Br, Wenbinhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1648795/tlv320aic3109-q1-please-provide-some-dts-related-configuration-information/6359800Wed, 27 May 2026 01:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:323a4d15-c335-46b5-a27d-565f6edd4b72lllya02 FfffIn addition, we plan to use the tlv320adc3101 ADC chip. May I ask if writing the device tree this way is problematic? If possible, could you also provide the device tree for the adc3101?https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1648795/tlv320aic3109-q1-please-provide-some-dts-related-configuration-information/6359790Wed, 27 May 2026 01:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5edcfeaa-0a97-4672-b7a0-26ec4042ef8elllya02 Fffftlv320aic3109_sound: tlv320aic3109-sound { status = &quot;okay&quot;; compatible = &quot;rockchip,multicodecs-card&quot;; rockchip,card-name = &quot;rk-tlv320aic3109&quot;; rockchip,cpu = ; rockchip,codec = ; rockchip,format = &quot;i2s&quot;; rockchip,mclk-fs = ; rockchip,audio-routing = &quot;Headphone&quot;, &quot;HPL&quot;, &quot;Headphone&quot;, &quot;HPR&quot;, &quot;Speaker&quot;, &quot;SPK&quot;, &quot;MIC1LP&quot;, &quot;Main Mic&quot;, &quot;MIC1RP&quot;, &quot;Main Mic&quot;; hp-det-gpio = ; io-channels = ; io-channel-names = &quot;adc-detect&quot;; keyup-threshold-microvolt = ; poll-interval = ; spk-con-gpio = ; hp-con-gpio = ; rockchip,pre-power-on-delay-ms = ; rockchip,post-power-down-delay-ms = ; pinctrl-names = &quot;default&quot;; pinctrl-0 = ; play-pause-key { label = &quot;playpause&quot;; linux,code = ; press-threshold-microvolt = ; }; }; &amp;i2c3 { status = &quot;okay&quot;; tlv320aic3109: tlv320aic3109@18 { status = &quot;okay&quot;; compatible = &quot;ti,tlv320aic310x&quot;; reg = ; #sound-dai-cells = ; clocks = ; clock-names = &quot;mclk&quot;; reset-gpios = ; AVDD-supply = ; IOVDD-supply = ; DVDD-supply = ; pinctrl-names = &quot;default&quot;; pinctrl-0 = ; }; }; &amp;sai1 { status = &quot;okay&quot;; pinctrl-names = &quot;default&quot;; pinctrl-0 = ; assigned-clocks = ; assigned-clock-rates = ; };请问我这样书写设备树会有问题吗https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1644806/tas5830-ppc3-pure-path-console-install-sw/6359726Tue, 26 May 2026 23:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c97ebbbf-a33a-4e60-9be3-fb84bede7d1aHan ParkHi Wenbin Li1 This morning, it&#39;s still pending. ㅠ.ㅠhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1647080/tas2505-low-audio-output-with-tas20505-digital-input-speaker-amplifier/6359724Tue, 26 May 2026 23:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8b3f2ebf-4c8f-4e01-8843-671bbaebad5fShenghao DingOne more thing, any log can be shared from following functions? tas2505_hw_params() tas2505_set_dai_fmt() tas2505_setup_pll()https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1647080/tas2505-low-audio-output-with-tas20505-digital-input-speaker-amplifier/6359722Tue, 26 May 2026 23:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:729dedc3-e0d0-48ee-aa51-523488677308Shenghao Ding[ 2.902181] tas2505-codec 4-0018: tas2505_set_dai_sysclk: clk_id: 0, freq: 133000000 [ 2.916243] tas2505-codec 4-0018: Can&#39;t produce required PLL_CLKIN frequency Can you ask platform vendor how to change 133000000 to 12288000?https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1647834/tas2770-click-and-pop-suppression/6359717Tue, 26 May 2026 23:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f2fc191d-f355-4cd5-87ad-6fb4597835d4Shenghao DingI&#39;m not sure, if our tas2770 do not support this, you can set them in the code. You can out tas2781-i2c.c code, all the register settings are stored in the bin file, you won&#39;t change any code.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1647080/tas2505-low-audio-output-with-tas20505-digital-input-speaker-amplifier/6359711Tue, 26 May 2026 23:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:443e368a-072d-4f88-bef8-033c55aa45e1Shenghao Ding[quote userid=&quot;460493&quot; url=&quot;~/support/audio-group/audio/f/audio-forum/1647080/tas2505-low-audio-output-with-tas20505-digital-input-speaker-amplifier/6353507&quot;] The applicaiton note is TAS2505 Application Reference Guide (Rev. C) D7~D6, in page 0, register 27. Pls try settting it as DSP, LJF, RJF during aplay the wav file. Let me know the result. Thanks. [/quote] Any feedback of this?https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1645862/tlv320aic3107-output-level-higher-than-agc-target-gain-setting/6359632Tue, 26 May 2026 22:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ccd6b9bc-f775-4db5-95fe-45ba43c6c32dMir JeffresHi, I tested today and am seeing something similar to you. I think there are a few things at play here, and we can do some more testing to narrow it down if you would like. First, it seems like the noise threshold is not correct, and is off in dB by a factor of 2 or 3, or maybe it just is set to one level, which I was measuring to be around -45dBFS (wrt 0.707Vrms as the full scale on the ADC single ended). At this input level, the AGC seemed to stop being engaged. I tested this with the noise gate at -30dB and -90dB and saw it behave the same for either setting. Another thing I noticed was that there were levels to the AGC behavior, where the input level determined what the output was, even within the range when the AGC was enabled. So, firstly, I noticed that the output of the ADC when AGC was enabled was typically around 6dB higher than we would expect based on the &quot;target level&quot;, so that is likely where you are seeing that ~5dB increase. But I was also seeing these levels change up, and there was only a small range in the inputs that led to the expected target level + 6dB being the output of the ADC. I did this sweep so you can see: we see that at -45dBrG (dBFS if we say ADC input 0dBFS is .707Vrms), the output jumps up to ~-4dBFS, which is -10dBFS + 6 (I have the target set to -10dBFS right now). Then it stays until around -33dBFS analog input, and it scales upwards until we hit around -26dBFS when it jumps down and scales upward until we hit -20dBFS when it gets stuck at -2dBFS output. This behavior being stuck at ~-2dBFS was seen with multiple target levels, it seems like maybe this is when the input goes OVER the target it needs, since it is extra distorted. Again I am not sure about how the algorithm actually works I just wanted to share with you that I am seeing this, and check if you are seeing this same behavior as well, so we can be on the same page. ^ when the output switches to the high gain -2dBFS output, when input hits ~-20dB ^ before it goes to the -2dBFS output, we see ~4dB output which is -10dB target level plus 5 or 6dB I will attach my code as well, I was using your script with a few changes to the clocking since I was not sure what you had set register 0x03 to and was using 12.288MHz MCLK, but not sure your MCLK. w 30 00 00 # w 30 01 00 w 30 01 80 #software reset w 30 02 00 # w 30 03 91 #defaults but pll enabled and p=1 w 30 03 11 #p = 1, pll disabled, q=2 w 30 04 04 #j = 1 # w 30 04 20 #j = 8 w 30 05 00 w 30 06 00 #d=0 # w 30 07 8A #44.1k, ldac plays l, rdac plays r w 30 07 0a #48k w 30 08 C0 #bclk and wclk are outputs (master mode) w 30 09 00 #i2s mode, 16 bit w 30 0A 00 # w 30 0B E1 #1110 0001 l+r adc overflow, ldac overflow. r= 1 w 30 0C 00 # w 30 0D 00 w 30 0E 00 w 30 0F 80 #00 #80 = ladc pga muted w 30 10 80 #00 #80 = radc pga muted w 30 11 FF w 30 12 FF w 30 13 04 #04 = single ended, level=0db, ladc powered up # w 30 13 84 #differential experiment w 30 14 78 w 30 15 00 #f8 #00=line1r single ended, f8 = lin1r differential and not connected to ladc pga. 00 means line1r is connected to ladc pga # w 30 15 80 #line1r is differential (experiment) w 30 16 7C #84 w 30 17 78 w 30 18 78 w 30 19 02 #micbias powered donw, reserved # w 30 1A C0 #lagc enabled, lagc target = -14db # w 30 1a 80 #lagc enabled, target = -5.5dB. measured around fulls cale # w 30 1a 90 #target = -8dB w 30 1a a0 #target = -10dB # w 30 1a 00 w 30 1B FE #max gain= max w 30 1C 00 #def noise gate, -30dB # w 30 1c 3e #noise threshold = -90dB # w 30 1D C0 #ragc enabled, target = -14dB # w 30 1E FE #max gain = max # w 30 1F 00 #f8 -&gt; f8 means hysteresis disabled and noise thresh -90db # w 30 20 F5 #left channel gain applied by agc = 1111 0101 (negative value I think) # w 30 21 77 #r channel gain applied = 0111 0111 = +59.5dB (max gain applied since it is noise) w 30 22 00 w 30 23 00 # w 30 24 45 #ladc powered up, not saturated, radc powered up, ragc gain = max allowed gain w 30 25 C0 #l+rdac powered up w 30 26 00 w 30 27 00 w 30 28 00 w 30 29 50 #ldac selects dac_l3 to left line output, rdac selects dac_r3 path to right w 30 2A 00 w 30 2B 00 w 30 2C 00 w 30 2D 00 w 30 2E 00 w 30 2F 00 w 30 30 00 w 30 31 00 w 30 32 00 w 30 33 04 #hplout is muted w 30 34 00 w 30 35 00 w 30 36 00 w 30 37 00 w 30 38 00 w 30 39 00 w 30 3A 04 #hpcom is muted w 30 3B 00 w 30 3C 00 w 30 3D 00 w 30 3E 00 w 30 3F 00 w 30 40 00 w 30 41 04 #hprout muted w 30 42 00 w 30 43 00 w 30 44 00 w 30 45 00 w 30 46 00 w 30 47 00 w 30 48 04 #reserved w 30 49 00 w 30 4A 00 w 30 4B 00 w 30 4C 00 w 30 4D 00 w 30 4E 00 w 30 4F 00 w 30 50 00 w 30 51 00 w 30 52 00 w 30 53 00 w 30 54 00 w 30 55 00 w 30 56 1B #0001 1011 left_lop output level = 1dB, not muted, not all gains have been applied, fully powere dup w 30 57 00 w 30 58 00 w 30 59 00 w 30 5A 00 w 30 5B 00 w 30 5C 00 w 30 5D 1B #r_lop output = 1dB, not muted, not all gains, fully powered up w 30 5E D8 #1101 1000 l+r dac powered up, l+r lop powered up w 30 5F 00 w 30 60 00 w 30 61 00 w 30 62 00 w 30 63 00 w 30 64 00 w 30 65 00 #codec_clkin uses plldiv_out w 30 66 02 #a0 -&gt; a0 = clkdiv_in uses bclk, pllclk_in uses bclk, but 0x02 is clkdiv and pllclk uses mclk # pll clock N = 2 w 30 67 00 w 30 68 00 w 30 69 00 w 30 6A 00 w 30 6B 00 w 30 6C 00 w 30 6D 00 Best, Mirhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1644668/tlv320aic34-reset-flush-output-of-tlv320ai34/6359449Tue, 26 May 2026 20:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7dca5017-1179-4d99-bac8-3476f4cf4258Luke EvansThanks for the suggestions. Register 9 sync option do change the behaviour, but it is less consistent this way. The first one is still different, and subsequent transfers are delayed by varying amounts. Short protection unfortunately doesn&#39;t make a difference with or without Sync options. I can take a look at keeping the clocks running. Any further suggestions would be welcome in the meantime.https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1648795/tlv320aic3109-q1-please-provide-some-dts-related-configuration-information/6359369Tue, 26 May 2026 19:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8656fec1-ee56-4e09-a8e2-90d1ff4e5ff5Mir JeffresHi, I have this file as tlv320aic31xx.txt in documentation: Texas Instruments - tlv320aic31xx Codec module The tlv320aic31xx serial control bus communicates through I2C protocols Required properties: - compatible - &quot;string&quot; - One of: &quot;ti,tlv320aic310x&quot; - Generic TLV320AIC31xx with mono speaker amp &quot;ti,tlv320aic311x&quot; - Generic TLV320AIC31xx with stereo speaker amp &quot;ti,tlv320aic3100&quot; - TLV320AIC3100 (mono speaker amp, no MiniDSP) &quot;ti,tlv320aic3110&quot; - TLV320AIC3110 (stereo speaker amp, no MiniDSP) &quot;ti,tlv320aic3120&quot; - TLV320AIC3120 (mono speaker amp, MiniDSP) &quot;ti,tlv320aic3111&quot; - TLV320AIC3111 (stereo speaker amp, MiniDSP) &quot;ti,tlv320dac3100&quot; - TLV320DAC3100 (no ADC, mono speaker amp, no MiniDSP) &quot;ti,tlv320dac3101&quot; - TLV320DAC3101 (no ADC, stereo speaker amp, no MiniDSP) - reg - - I2C slave address - HPVDD-supply, SPRVDD-supply, SPLVDD-supply, AVDD-supply, IOVDD-supply, DVDD-supply : power supplies for the device as covered in Documentation/devicetree/bindings/regulator/regulator.txt Optional properties: - reset-gpios - GPIO specification for the active low RESET input. - ai31xx-micbias-vg - MicBias Voltage setting 1 or MICBIAS_2_0V - MICBIAS output is powered to 2.0V 2 or MICBIAS_2_5V - MICBIAS output is powered to 2.5V 3 or MICBIAS_AVDD - MICBIAS output is connected to AVDD If this node is not mentioned or if the value is unknown, then micbias is set to 2.0V. Deprecated properties: - gpio-reset - gpio pin number used for codec reset CODEC output pins: * HPL * HPR * SPL, devices with stereo speaker amp * SPR, devices with stereo speaker amp * SPK, devices with mono speaker amp * MICBIAS CODEC input pins: * MIC1LP, devices with ADC * MIC1RP, devices with ADC * MIC1LM, devices with ADC * AIN1, devices without ADC * AIN2, devices without ADC The pins can be used in referring sound node&#39;s audio-routing property. Example: #include #include tlv320aic31xx: tlv320aic31xx@18 { compatible = &quot;ti,tlv320aic311x&quot;; reg = ; ai31xx-micbias-vg = ; reset-gpios = ; HPVDD-supply = ; SPRVDD-supply = ; SPLVDD-supply = ; AVDD-supply = ; IOVDD-supply = ; DVDD-supply = ; }; Let me know if you need more specific help. Best, Mirhttps://e2e.ti.com/support/audio-group/audio/f/audio-forum/1649069/tlv320adc3140-lv320adc3140-5140-exact-vcom-bias-for-dc-coupled-mode-vref-2-75v/6359258Tue, 26 May 2026 18:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2a19e018-da63-4405-8b76-dc29ad287176Garret GodfreyHello, The input should be biased to support the full swing between 0V and AVDD. 1Vrms single-ended and 2vrms differential need a 1.414V bias to ensure the signal does not clip below 0. 1.375V at a minimum should be close enough to support this for AVDD=3.3V, but above 1.4V would be better. Best, Garret