This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • Resolved

TAS5538 Location of Input/Output Automute

Guru 30225 points

Replies: 46

Views: 4385

Hi,

Could you please tell us each location of the input and output automute functions in the block diagram as below?

Best Regards,
Kato

  • In reply to Sadanori Kato:

    Hi Tuan-san,

    I have one more question as below.

    3. When Asserting D1 of the register 0x05~0x0C to high
    How does TAS5538 work if the D1 of register 0x05~0x0C is asserted to high?
    The noise occurs during the reproduction of the low frequency data if the D1 is asserted to low in the BD mode.
    However, that noise is improved if the D1 is asserted to high and the value of the register 0x38~0x03F which is 8 interchannel channel delay registers is adjusted.
    Could you please tell us that technical operation mechanism?

    Best Regards,
    Kato

  • In reply to Sadanori Kato:

    Hello Tuan-san, team,

    Can you please update this plate for Kato-san?

    We are facing at a big complain from customer since our response is extremely slow.

    We need to update cutomer by tomorrow so please help us to proceed the case otherwise there would be no way that we say US site is shut off now due to xmas holiday period.

    Hope we can hear from you.

    Thank you and best regards,

    Daisuke KAWASAKI

  • In reply to daisuke kawasaki:

    Hi Tuan-san,

    Could you please update regarding the following questions since I have to reply the information to our customer by January 5(JST)?

    1. When Asserting D6 and D5 of the register 0x04 to high
    How does TAS5538 work if the D6 and D5 of the register 0x04 is asserted to high?
    Is my understanding correct although I believe that nothing changes?

    2. When Asserting the reserved bits of the register 0x05~0x0C to high
    How does TAS5538 work if the reserved bits of the register 0x05~0x0C is asserted to high, except D4 and D7?

    3. When Asserting D1 of the register 0x05~0x0C to high
    How does TAS5538 work if the D1 of register 0x05~0x0C is asserted to high?
    The noise occurs during the reproduction of the low frequency data if the D1 is asserted to low in the BD mode.
    However, that noise is improved if the D1 is asserted to high and the value of the register 0x38~0x03F which is 8 interchannel channel delay registers is adjusted.
    Could you please tell us that technical operation mechanism?

    Best Regards,
    Kato

  • In reply to Sadanori Kato:

    Hello Kato-san,
    Happy New Year. Sorry, I was on vacation and couldn't answer your question sooner.
    1. As mentioned in previous post, these should be reserved registers since the function was not implemented. The designers may have used it for interal parameters or other uses. Please do not change the default settings. It may not affect anything. However in some conditions, the designers may use them for internal usage.
    2. Again, reserved bits should not be altered. Please keep the default settings.
    3. This bit is also reserved. In transition from TAS5508C to TAS5538, the designer may have used it for internal usage and is not meant for the customer's usage. Please keep this in default setting.
    Best regards,Tuan

    Automotive Audio Applications

    Texas Instruments, Inc.

    [TI makes no warranties and assumes no liability for applications assistance or customer product design. You are fully responsible for all design decisions and engineering with regard to your products, including decisions relating to application of TI products. By providing technical information, TI does not intend to offer or provide engineering services or advice concerning your designs.]

  • In reply to Tuan:

    Hi Tuan-san,

    Happy New Year.
    Thank you always for your kind support.
    Could you please share more detailed technical information if possible since our customer does not readily understand regarding Q1 and Q3?

    Best Regards,
    Kato

  • In reply to Sadanori Kato:

    Hi Tuan-san,

    I have discussed with our customers based on your response, this issue has been closed.
    However, I will post an additional question since I have obtained a new question from them.
    I greatly appreciate your cooperation.

    Best Regards,
    Kato

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.