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AIC3106 Pop Noise on Lineout

Robert Eschler
Guru 52335 points

We use the AIC3106 audio codec on our EVM, and are having and issue.  There is a ‘pop’ noise when the device is enabled, and we are unable to explain/get rid of it.  We have captured some waveforms and would like to understand cause of voltage spike so we can get rid of it.  The image below is capture on the LINEOUT +/- pins.

 

Thanks
Robert

  • 0
    TI__Mastermind 28585 points

    Hi Robert,

    Pop is very dependent on hardware and register configuration. Can you forward the schematics and registers that are being written (and the sequence of writes).

    Thanks,

    dave

  • 0 in reply to Converter Apps
    TI__Guru 52335 points

    Dave,

    Here is schematic:

    8787.516582E_VAYU_EVM_05AUG_2013B_AIC3106.pdf

    These are the register writes done to enable LineOut. I added a delay between the writes to identify which register was causing the pop:

    Register 37 = 0x0c

    Register 86 = 0x01   <- Causes pop on left channel

    Register 93 = 0x01   <- Causes pop on right channel

     

    Initial state (before the three writes shown above) was:

     

    |----------------------------------------------------------------|

    | Reg. Name                              | Reg. Addr | Reg. Val. |

    |----------------------------------------------------------------|

    | Page Select                            |   0       | 0x00      |

    | Software Reset                         |   1       | 0x00      |

    | Codec Sample Rate Select               |   2       | 0x00      |

    | PLL Programming A                      |   3       | 0x91      |

    | PLL Programming B                      |   4       | 0x40      |

    | PLL Programming C                      |   5       | 0x00      |

    | PLL Programming D                      |   6       | 0x00      |

    | Codec Datapath Setup                   |   7       | 0x8A      |

    | Audio Serial Data Interface Control A  |   8       | 0x00      |

    | Audio Serial Data Interface Control B  |   9       | 0x00      |

    | Audio Serial Data Interface Control B  |  10       | 0x00      |

    | Audio Codec Overflow Flag              |  11       | 0x01      |

    | Audio Codec Digital Filter Control     |  12       | 0x00      |

    | Headset / Button Press Detection A     |  13       | 0x00      |

    | Headset / Button Press Detection B     |  14       | 0x00      |

    | Left ADC PGA Gain Control              |  15       | 0x80      |

    | Right ADC PGA Gain Control             |  16       | 0x80      |

    | MIC3L/R to Left ADC Control            |  17       | 0xFF      |

    | MIC3L/R to Right ADC Control           |  18       | 0xFF      |

    | LINE1L to Left ADC Control             |  19       | 0x78      |

    | LINE2L to Left ADC Control             |  20       | 0x78      |

    | LINE1R to Left ADC Control             |  21       | 0x78      |

    | LINE1R to Right ADC Control            |  22       | 0x78      |

    | LINE2R to Right ADC Control            |  23       | 0x78      |

    | LINE1L to Right ADC Control            |  24       | 0x78      |

    | MICBIAS Control                        |  25       | 0x06      |

    | Left AGC Control A                     |  26       | 0x00      |

    | Left AGC Control B                     |  27       | 0xFE      |

    | Left AGC Control C                     |  28       | 0x00      |

    | Right AGC Control A                    |  29       | 0x00      |

    | Right AGC Control B                    |  30       | 0xFE      |

    | Right AGC Control C                    |  31       | 0x00      |

    | Left AGC Gain                          |  32       | 0x00      |

    | Right AGC Gain                         |  33       | 0x20      |

    | Left AGC Noise Gate Debounce           |  34       | 0x00      |

    | Right AGC Noise Gate Debounce          |  35       | 0x00      |

    | ADC Flag                               |  36       | 0x02      |

    | DAC Power and Output Driver Control    |  37       | 0x00      |

    | High-Power Output Driver Control       |  38       | 0x00      |

    | High Power Output Stage Control        |  40       | 0x00      |

    | DAC Output Switching Control           |  41       | 0x00      |

    | Output Driver Pop Reduction            |  42       | 0x00      |

    | Left DAC Digital Volume Control        |  43       | 0x7F      |

    | Right DAC Digital Volume Control       |  44       | 0x7F      |

    | LINE2L to HPLOUT Volume Control        |  45       | 0x76      |

    | PGA_L to HPLOUT Volume Control         |  46       | 0x76      |

    | DAC_L1 to HPLOUT Volume Control        |  47       | 0x76      |

    | LINE2R to HPLOUT Volume Control        |  48       | 0x76      |

    | PGA_R to HPLOUT Volume Control         |  49       | 0x76      |

    | DAC_R1 to HPLOUT Volume Control        |  50       | 0x76      |

    | HPLOUT Output Level Control            |  51       | 0x04      |

    | LINE2L to HPLCOM Volume Control        |  52       | 0x76      |

    | PGA_L to HPLCOM Volume Control         |  53       | 0x76      |

    | DAC_L1 to HPLCOM Volume Control        |  54       | 0x76      |

    | LINE2R to HPLCOM Volume Control        |  55       | 0x76      |

    | PGA_R to HPLCOM Volume Control         |  56       | 0x76      |

    | DAC_R1 to HPLCOM Volume Control        |  57       | 0x76      |

    | HPLCOM Output Level Control            |  58       | 0x04      |

    | LINE2L to HPROUT Volume Control        |  59       | 0x76      |

    | PGA_L to HPROUT Volume Control         |  60       | 0x76      |

    | DAC_L1 to HPROUT Volume Control        |  61       | 0x76      |

    | LINE2R to HPROUT Volume Control        |  62       | 0x76      |

    | PGA_R to HPROUT Volume Control         |  63       | 0x76      |

    | DAC_R1 to HPROUT Volume Control        |  64       | 0x76      |

    | HPROUT Output Level Control            |  65       | 0x04      |

    | LINE2L to HPRCOM Volume Control        |  66       | 0x76      |

    | PGA_L to HPRCOM Volume Control         |  67       | 0x76      |

    | DAC_L1 to HPRCOM Volume Control        |  68       | 0x76      |

    | LINE2R to HPRCOM Volume Control        |  69       | 0x76      |

    | PGA_R to HPRCOM Volume Control         |  70       | 0x76      |

    | DAC_R1 to HPRCOM Volume Control        |  71       | 0x76      |

    | HPRCOM Output Level Control            |  72       | 0x04      |

    | LINE2L to MONO_LOP/M Volume Control    |  73       | 0x76      |

    | PGA_L to MONO_LOP/M Volume Control     |  74       | 0x76      |

    | DAC_L1 to MONO_LOP/M Volume Control    |  75       | 0x76      |

    | LINE2R to MONO_LOP/M Volume Control    |  76       | 0x76      |

    | PGA_R to MONO_LOP/M Volume Control     |  77       | 0x76      |

    | DAC_R1 to MONO_LOP/M Volume Control    |  78       | 0x76      |

    | MONO_LOP/M Output Level Control        |  79       | 0x00      |

    | LINE2L to LEFT_LOP/M Volume Control    |  80       | 0x76      |

    | PGA_L to LEFT_LOP/M Volume Control     |  81       | 0x76      |

    | DAC_L1 to LEFT_LOP/M Volume Control    |  82       | 0x76      |

    | LINE2R to LEFT_LOP/M Volume Control    |  83       | 0x76      |

    | PGA_R to LEFT_LOP/M Volume Control     |  84       | 0x76      |

    | DAC_R1 to LEFT_LOP/M Volume Control    |  85       | 0x76      |

    | LEFT_LOP/M Output Level Control        |  86       | 0x00      |

    | LINE2L to RIGHT_LOP/M Volume Control   |  87       | 0x76      |

    | PGA_L to RIGHT_LOP/M Volume Control    |  88       | 0x76      |

    | DAC_L1 to RIGHT_LOP/M Volume Control   |  89       | 0x76      |

    | LINE2R to RIGHT_LOP/M Volume Control   |  90       | 0x76      |

    | PGA_R to RIGHT_LOP/M Volume Control    |  91       | 0x76      |

    | DAC_R1 to RIGHT_LOP/M Volume Control   |  92       | 0x76      |

    | RIGHT_LOP/M Output Level Control       |  93       | 0x00      |

    | Module Power Status                    |  94       | 0x00      |

    | Output Driver Short Circuit Detection  |  95       | 0x00      |

    | Sticky Interrupt Flags                 |  96       | 0x00      |

    | Real-Time Interrupt Flags              |  97       | 0x01      |

    | GPIO1 Control                          |  98       | 0x00      |

    | GPIO2 Control                          |  99       | 0x00      |

    | Additional GPIO Control A              | 100       | 0x00      |

    | Additional GPIO Control B              | 101       | 0x00      |

    | Clock Generation Control               | 102       | 0x02      |

    | Left AGC New Programmable Attack Time  | 103       | 0x00      |

    | Left AGC New Programmable Decay Time   | 104       | 0x00      |

    | Right AGC New Programmable Attack Time | 105       | 0x00      |

    | Right AGC New Programmable Decay Time  | 106       | 0x00      |

    | New Programmable ADC Digital Path      | 107       | 0x00      |

    | Passive Analog Signal Bypass Selection | 108       | 0x00      |

    | DAC Quiescent Current Adjustment       | 109       | 0x00      |

    |----------------------------------------------------------------|

     

  • 0 in reply to Robert Eschler
    TI__Mastermind 28585 points

    Hi Robert,

    About the only thing you can do with the line outputs is try going differential. Since the pop signal is the same on both outputs +/-, it would tend to cancel.

    The HP outputs have several pop reduction registers but since it is assumed that the line outputs will be driving a separate amplifier stage, it is up to the amp stage to handle the pop reduction (i.e. don't power up the amp stage until after the line outputs are stable).

    Best Regards,

    dave