If I am feeding in data at 8K SPS and the Sample Rate Control (Address: 0001000) is set for Normal mode at 256Fs, it seems that MCLK should be 2.048MHz . I do not see how to resolve the SRx bits in that regiater for an MCLK this low.
Can you help me?
What if I made the TI chip the master on the DCI port? MCLK = ?