Hi all!
I think the TAS5756M is a great device - it's easy to work with, extremely flexible, good sounding, powerful, very eficient and can run on comparably low voltages.
In this post I've written a few things down from my own personal experience in working with the part (over i2c using some unmentionable micro controller*) that I found possibly represent mismatches between what is described in the current (initial) version of the d/s and the h/w revision that I was using up to the time of writing this.
As such, the below might or might not be true depending on the d/s and/or h/w revision at hand - and, I could of course also simply be mistaken so consider this a live list in until verified by TI employees or others.
Still, here's a summary of what I have found so far:
1. When programming the PLL, clock dividers etc, dont forget to first disable "auto clock mode" using P0-R37 and also to, if needed, ignore error detection on any non-present or invalid external clocks.
2. Selecting register page is not mentioned in the d/s but can be done by writing to the supposed page select register "P0-R0" specifying the requested register page number to set. This page selection register is (or seem to be) mapped onto all register pages and made availale as the zero position (first) register in each register page.
3. At system startup (host boot), be sure to first select register page zero (0) as mentioned above and then issue a reset by setting the appropriate bits of register P0-R1, before proceeding to programming the device - do not rely on register page being reset to zero without performing a power cycle.
You might also want to decrease the volume a bit since 0dB (0x3030) could be surprising :-)
4. The 10% (0.8dB) analogue gain boost register P1-R7 does not seem to have any effect or at least does not work as described in the d/s on page 83.
5. To select SCLK as the PLL reference, you should write the value 001 to register P0-R13[6:4]. The d/s incorrectly says MCLK for both values 000 and 001.
6. Figure 63 on page 36 in the d/s does not seem to reflect all the settings claimed possible by the DAC clock source register P0-R14.
7. The SLCK Fs factor register P0-R93 described (somewhat awkwardly) on page 79 in the d/s also claims to contain the MCLK ratio, This looks to be incorrect, instead the MCLK Fs factor can only be read using register P0-R91.
8. The DSP program selection (different filters etc) register only seem to result in sound being produced for values 1 and 2 while other values result in dead silence.
9. The miniDSP DSP core is barely covered and the referred-to document "TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577)", first mentioned on page 88, is not yet available at the time of writing.
10. Switching frequency settings using a voltage divider as described on page 53 in the d/s incorrectly states factors 2, 4, 6, and 8 times Fsync but in reality, these factors are 4, 5, 6 and 8 times Fsync. See this post:
11. The PLL locked flag (bit 5) of register P0-R94 is inverted in the d/s, in reality 0 means PLL is locked. You can just as well use P0-R4[4]. See this post:
12. Section 8.4.2.54 on page 81 is incorrectly titled "P0-R117" as it actually describes register P0-R118.
Thank you and have a nice day!
*) Commonly mistaken for a dessert, eg not the TI EVM and GUI,.
