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PCM3168 and mcasp0 of sitara processor (BeagleBoneBlack)

Pablo Fonovich
Intellectual 765 points
Other Parts Discussed in Thread: PCM3168A-Q1, PCM3168, PLL1707

Hi:

Im designing a multichannel audio cape for BeagleBoneBlack, using the PCM3168A-Q1...

I wanted to ask if i should connect SCKI of the codec to an externall codec or if there is a pin of the mcasp0 for this function?

Can someone give me some example schematic of how clock's in the codec shoul be implemented?

I've already connected the sitara's mcasp0_aclkr (P9_42 on BBB) to the BCLKAD pin in the codec; the mcasp0_aclkx (P9_31) to the BCLKDA pin of the codec; mcasp0_fsr (P9_27) to the LRCLKAD of the codec and the mcasp0_fsx (P9_27) to the LRCLKDA of the codec. Is that OK?

mcasp0_ahclkr or the mcasp0_ahclkx can be used for SCKI?

thanks

  • 0
    Intellectual 765 points
    Hi:
    As nobody answered, i'll propose a solution, and i want to ask if it's ok...
    what if i use PLL1707 to generate the clock and connect it to SCKI of the PCM3168? Should i also connect it to mcasp0_ahclkr and the mcasp0_ahclkx to syncrhonize it all (selecting them as input)?

    Please help me... i need to know where to get the clock for SCKI... i can't find it on datasheets, and i don't know if the mcasp of the processor already has a pin for this...
  • 0 in reply to Pablo Fonovich
    TI__Mastermind 27850 points

    Hi Pablo,

    I don't know too much about the McASP port since I am in the audio group, so more detailed questions should be posted to the sitara forum. What I can tell you is that the signals are explained pretty well in the AM335X reference guide in the McASP section. The X/R at the end of the name designates transmit or receive. When using audio codecs there are usually multiple ways to configure the clocking, but in most cases the clock signals, BCK, FSCK, and SCKI need to be synchronous for the part to operate reliably. If the part is operating as a master, then a crystal or stand alone clokcing IC can be used as the codec will generate its signals from the SCKI internally. If the codec is operating in slave mode, and have a crystal or stand alone clock ic supply the SCKI and the other clock signals come from the AM335x, the clocks most likely are not synchronous, and would cause reliability issues. In a situation where the codec is a slave, it would be best to get all clocks from the master device. The ACHCK from the McASP port can be used as the SCKI signal, but you must make sure that it will be at an acceptable rate in relation to fs (128fs, 192fs, 256fs, 384fs, 512fs, or 768fs) . The McASP signals relate to audio signals as follows:

    McASP Audio
    ACLK Bit clock (BCK)
    fs frame sync (LRCK)
    AHCLK Main clock (MCLK or SCKI)
    AXR data

    Justin

  • 0 in reply to Justin Bohr
    Intellectual 765 points
    Thanks very much... that's pretty much what i wanted to ask...

    I've already asked in the sitara forums and they send me here... they gave me hints about device tree's and so on... but not about phisical conection...

    I've read de AM335X datasheet and TRM... i think i understand the meaning of the pins in the mcasp... in my first post i asked about using mcasp0_ahclkr or the mcasp0_ahclkx... i know x is for transmit and r for recieve, but i only have one SCKI in the codec... so which one should i use? mcasp0_ahclkr or the mcasp0_ahclkx?

    then i read about using mcasp something like hybrid... with mcasp0_ahclkr and the mcasp0_ahclkx as inputs and the rest as outputs... and that's why i asked the next question about the PLL

    If i use mcasp0_ahclkr for SCKI, then i don't know if the transmission from codec to beaglebone will be synchronized... the other way round if i decide to use mcasp0_ahclkx for SCKI... Can i use any of them? I want to use the codec as slave by the way...