PCM1802 - Power-On Reset Sequence

Hi all 

Would you mind if we ask Power-On Reset Sequence of PCM1802 which shows on the datasheet P14? 

<Q1>
According to Codec type, it is required to toggle(switch low, high) Power down at the first power sequence.
About PCM1802, is it required to toggle(switch low, high) PDWN pin at the first power sequence?

<Q2>
Is it required to be inputted System Clocks signal before VDD is switched on as the datasheet P14?
Because our customer' power sequence is followings;
-First: VDD on
-Second: Clock in.

<Q3>
About 4480 / fs, does this "fs" mean 256 fs(depending on "INTERFACE MODE")? or 11.2896MHz?

<Q4>
During Power-On Reset Sequence, of course we use VinL and VinR have to keep high impedance using AC coupling.
About high impedance, how much is the value of it? 1Mohm?

We appreciate your help.

Kind regards,

Hirotaka Matsumoto