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PCM1781 (or any I2S DAC) clock sources


I'm just trying to understand the best way to derive the bit clock and LR clock from the master clock; I think this is relevant for just about any I2S DAC, but Google is drowning me in everything but answers. The ADC I have works in master mode, taking only master clock as input, but that works because it doesn't need digital input.

The datasheet tells me I can buy a PLL17** chip from TI for the master clock, great! But then, in order for the data to be synchronized with the LR and bit clocks, is it necessary for my MCU to do all the calculating? Do I then need to buy separate frequency divider chips to get the LR and bit clocks from the master clock?

I gather, then, that my MCU or audio processor needs to take at least the LR and bit clocks as input in order to synchronize its data output to them.

So, in order to get audio output from an MCU, do I really need 1. a DAC chip; 2. a clock generator; 3. a clock divider; 4. another clock divider; and 5. the MCU itself?? 5 chips to do digital to analog conversion?

Thanks for any guidance. I assure you I've been combing the internet and Google for many days for this info.


5 Replies

  • Hi Chuck,

    Depending on the ICs involved in the system there are many paths to getting a audio converter path to work. Most converters we have, DACs, ADCs, or codecs, will operate with an I2S interface. Usually what is needed is an external source for master clock (also called system clock). If the audio device being used will be the master, it will take the provided master clock and create the BCK and LRCK clocks. This will result in the master clock, LRCK, BCK, and data being synchronous, as well as BCK, LRCK, and data being in phase. This will allow the audio transmission to work correctly. These clocks will then be output from the audio IC to the device that will receive the I2S. In this scenario, the MCU/DSP/FPGA will need to be able to accept an I2S interface. This means at least an input for LRCK, BCK and data. Many will want the master clock input as well.

    In summary the ideal setup will be 3 things, host processor, audio converter, and a master clock source. Some host processors will be able to provide the master clock, and might even have a restriction of needing to be the master. This should not be an issue as our devices can also operate as I2S slaves.

    There should be no need for external dividers.

  • In reply to Justin Bohr:

    Hi, Justin.

    The PCM1781 can only operate as slave. So I need to send it 3 different clocks and the data has to be synced to them, no exceptions. So my mcu has to either receive or produce all of them. I can either use cpu generating clocks that maynot be very accurate, or use 3 separate external sources. Am I missing something?

  • In reply to Charles Hubbard:

    Hi Chuck,

    It seems you are correct, if you are using an MCU that does not have a dedicated I2S interface, and a DAC that can be slave only you will need to create your own external clocks for all three clocks, unless you wanted to bit bang clocks from the MCU. You could use a DAC like the PCM5101A which gets you the same SNR performance and easy H/W configuration, but can operate in master mode, solving your clock generation issues.

  • In reply to Justin Bohr:

    Hi, Justin.

    I think I'm not being clear. My mcu does have an i2s interface, but the master clock required for the PCM1781 is NOT part of the i2s standard, and it is required to be at least 256x the sample rate and synchronized to the data. So it is in fact the DAC that requires non- i2s operation, not the mcu. The master clock is not part of the standard, so no one feels obligated to implement it, but for the data to be synchronized to it, it must go through the mcu at some point. I guess a 3rd possibility would be that an external master clock enters the mcu, which calculates the other clocks and sends them all to the DAC. I don't have the option of sending the master clock only to the dac and the i2s clocks from the mcu. My thought is to minimize the burden on the mcu (it also has to calculate the audio) by having it respond to the 2 i2s clocks instead of generating them, in which case the 2 i2s clocks and the non-i2s master clock have to come from 3rd, 4th and 5th parties, which have to all be in sync, hence, dividers. On the other hand, I have read that i2s requires 1 slave and 1 master, though I don't see how either slave would know that the other is not the master.
    So, 3 options:
    1. mcu calculates all clocks plus data, including the non-i2s master clock;
    2. Mcu receives master clock and calculates the i2s clocks and data; or
    3. All 3 clocks are generated externally.

    How do people usually do this?? Or
    4. Non-i2s master clock and i2s bit clock are generated externally, mcu generates lrclock and data?

    Thanks for your time.
  • In reply to Charles Hubbard:

    A late reply, perhaps it can help.

    True, the master (modulator) clock is not part of the I2S standard, which really only defines the audio serial port (data, bit clock synchronous to data, LRCLK to indicate which channel and also the start of a data frame). That said, in all cases that master clock must be a multiple of the sampling frequency, and 128 * Fs, 256 * Fs and 512 * Fs are common multiples. Thus you'll often see a 24.576 MHz master clock for 48 kHz (or 96 kHz) sampling.

    You haven't told us which MCU you're using. Some can synthesize the MCLK in an internal PLL. Others have an input which can take in the MCLK and divide it down generate provide LRCLK and BCLK (synchronous to the data) from it. And still others don't know anything about the MCLK, and can take from some external source LRCLK and BCLK as inputs and provide the data synchronous to BCLK.

    As Justin notes, PCM1781 is an I2S slave only, meaning some outside master must provide the BCLK and LRCLK along with the data. If your MCU's I2S port can't source those clocks synchronously with an MCLK (again, either synthesized by the MCU or provided to the MCU as an input), then the PCM1781 isn't a good choice. The PCM5101A can synthesize MCLK internally from input LRCLK, so as long as your MCU can provide LRCLK at (say) 48 kHz and BCLK at 64 * LRCLK, then it will work.

    Another option is to use a CPLD or some TTL logic to divide an oscillator at MCLK frequency down to the required BCLK and LRCLK rates and provide those to both the MCU and the DAC. You will also drive the DAC's MCLK input from that oscillator. (Remember that while the BCLK and LRCLK are synchronous to MCLK, the phase between MCLK and the other two doesn't really matter.)

    Hope this helps.

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