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TLV320AIC3101EVM-K setup issue

Other Parts Discussed in Thread: TLV320AIC3101EVM-K

team,

                GUI shows the EVM as being connected, but changing the role of bclk doesnt seem to work as bclk keeps on coming out (even when configured as input).

                Plus when unplugging the USB, GUI still sees the EVM connected and he still doesn’t get i2c read/write errors.

                I’m going to get myself an EVM but it’s going to be too late.

  • Hello, Olivier,

    Regarding the GUI issue when the EVM is unplugged, this seems to be a bug in the GUI. Effectively the GUI indicates that the EVM is still plugged if it is disconnected. Even with the indicator button, the result is the same.

    Regarding the BCLK issue, could you provide more details? Do you mean that the GUI doesn’t work if the BCLK is configured as output?

    Best regards,
    Luis Fernando Rodríguez S.
  • Fernando,
     
    Thanks for the bug report.
     
     
    This is right. Toggling blck role from out to in  in gui doesn’t seem to have any effect: Bclk is still present although it is programmed as an input.
     
    Olivier Mellin
    Texas Instruments France
    Senior Application Engineer
    65, quai G Gorse
    92650 Boulogne-Billancourt
    +33 6 74 08 75 5
     
    De : Luis Fernando Rodríguez S.
    Envoyé le :lundi 17 octobre 2016 17:26
    À : AudioConvertersForum@mail.e2e.ti.com
    Objet :Audio Converters Forum: TLV320AIC3101EVM-K setup issue
     

     

    A Message from the TI E2E™ Community
    Texas Instruments

     

    Luis Fernando Rodríguez S. replied to TLV320AIC3101EVM-K setup issue.

    Hello, Olivier,

    Regarding the GUI issue when the EVM is unplugged, this seems to be a bug in the GUI. Effectively the GUI indicates that the EVM is still plugged if it is disconnected. Even with the indicator button, the result is the same.

    Regarding the BCLK issue, could you provide more details? Do you mean that the GUI doesn’t work if the BCLK is configured as output?

    Best regards,
    Luis Fernando Rodríguez S.

     

     

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  • Hi, Olivier,

    The I2S lines are generated by the TAS1020b component on the EVM. When BCLK is configured as output, it is necessary to disable the USB I2S option on switch SW2 of the USB-MODEVM INTERFACE board. This disables the I2S lines from the TAS1020b and allows the EVM to be configured as master (BCLK and WCLK as outputs).

    So, even if the GUI configures the AIC3101 as input, the TAS1020b generates the I2S lines.

    Best regards,
    Luis Fernando Rodríguez S.
  • LUIS Frenando,

    Can you please advise a easy to check that the ui communicates correctly with rhe evm?

    Thanks

  • Hi, Olivier,

    The easiest way to verify if the EVM and GUI communicates correctly is by the preset configurations of GUI. I would recommend to try with a playback application, you only require to play an audio file with the computer. This configuration only works with the device in slave mode and the TAS1020b clock signals enabled. If you require external clock signals, the TAS1020b clock signals should be disabled (SW2 in MODEVM-INTERFACE board) and the external device should send the audio data via I2S.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando,


    I am the customer for whom Oliver is doing the interface.

    I have given up using the GUI. I drive the board with a PC I2C interface. I2S master clock, bit clock and frame clock are also fed externally, with appropriately set SW2. Current status is:

    - ADC works so-so: waveform is not correct but something happens

    - DAC not working at all

    Concerning the DAC, I want to output to lineout. Here is how I program the codec registers (lines starting with # are comments):

        #reg, value
    
        ## Page zero
        0, 0,
    
        ## Codec Sample Rate
        ## fs(ref)/1 for ADC and DAC
        2, 0, #default
    
        ## PLL reg A
        ## D7=0 PLL disabled
        ## D6-D3=0010 Q=2
        3, 0x10, #default
    
        ## Codec data-path
        ## D7=0 fs(ref) 48kHz
        ## D6-D5=11 ADC and DAC dual rate
        ## D4-D3=01 left DAC enabled
        ## D2-D1=01 right DAC enabled
        ## D0=0 reserved
        7, 0x6A,
    
        ## Serial IF reg A
        ## D7=0 BCLK slave
        ## D6=0 WCLK slave
        ## D5=0 No TDM
        ## D4=0 Don't care
        ## D3=0 Reserved
        ## D2=0 No 3D
        ## D1-D0=0 reserved
        8, 0,   #default
    
        #### Serial IF reg B
        ## D7-D6=00 I2S
        ## D5-D4=10 24bits
        ## D3=0 don't care
        ## D2=0 what's the use of this (default)
        ## D1=0 what's the use of this (default)
        ## D0=0 don't care
        9, 0x20,
    
        #### Serial IF reg C
        ## Data offset 1
        10, 0x01,
    
        #### Left ADC PGA gain
        ## D7=0 enabled
        ## D6-D0=0000000 0dB (to try)
        15, 0,
    
        #### Right ADC PGA gain
        ## D7=0 enabled
        ## D6-D0=0000000 0dB (to try)
        16, 0,
    
        #### LINE2 to left ADC
        ## D7-D4=0 LINE2L connected to left ADC
        ## D3-D0=F LINE2R not connected
        #17, 0x0F,
    
        #### LINE2 to right ADC
        ## D7-D4=F LINE2L not connected 
        ## D3-D0=0 LINE2R connected to right ADC
        #18, 0xF0,
    
        #### LINE1LP Left ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F LINE1LP not connected
        ## D2=1 left ADC up
        ## D1-D0=00 (default, don't care) 
        #19, 0x7C,
        19, 0x04,
    
        #### LINE1RP to left ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2-D0=0 reserved (default) 
        #21, 0,
    
        #### LINE1RP to right ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2=1 right ADC up
        ## D1-D0=0 (default, don't care) 
        #22, 0x7C,
        22, 0x04,
    
        #### LINE1LP to right ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2-D0=0 reserved (default) 
        #22, 0,
    
        #### DAC power
        ## D7-D6=11 Left and right DACs up
        37, 0xC0,
    
        #### DAC output switching
        ## D7-D6=01 DAC_L3 direct connection of DAC to lineout
        ## D5-D4=01 DAC_R3 direct connection of DAC to lineout
        41, 0x50,
        ## DAC_R1 and DAC_L1
        #41, 0x0,
        ## DAC_R2 and DAC_L2
        #41, 0xC0,
    
        #### Left DAC digital volume
        ## D7=0 unmute
        #43, 0,
    
        #### Right DAC digital volume
        ## D7=0 unmute
        #44, 0,
    
        ## DAC_L1 to LEFT_LOP
        #82, 0x80,
        ## DAC_R1 to RIGHT_LOP
        #92, 0x80,
    
        ## PGA_L to LEFT_LOP
        #81, 0x80,
        ## PGA_R to RIGHT_LOP
        #91, 0x80,
    
        #### LEFT_LOP output level
        ## D7-D4=0000 0dB
        ## D3=1 unmuted
        86, 0x08,
    
        #### RIGHT_LOP output level
        ## D7-D4=0000 0dB
        ## D3=1 unmuted
        93, 0x08,
    
        #### Clock register
        ## D0=1 ext clock
        101, 1,
    
        #### Clock generation
        ## D7-D6=00 CLKDIV_IN uses MCLK (default)
        102, 0, # default
    
        #109: try hight current mode

    Codec is always reset before programming with register 1 D7. Registers are read back by the program to check written value. Then I can then read a few registers for debugging:

    Read 11: 01
    Read 32: 00
    Read 33: 00
    Read 36: cc
    Read 86: 08  should be 09
    Read 93: 08  should be 09
    Read 94: c0  should be d8
    Read 95: 00
    Read 96: 00
    Read 97: 00

    So it appears the lineout drivers are off. Can you see what is going on? Should I write register 93 D0, although speced as read-only?


    Finally, there is a complete register dump below my signature. Could not attach a file (causing my browser to hang).


    Best regards,

    Jerome.

    Read 0: 00
    Read 1: 00
    Read 2: 00
    Read 3: 10
    Read 4: 04
    Read 5: 00
    Read 6: 00
    Read 7: 6a
    Read 8: 00
    Read 9: 20
    Read 10: 01
    Read 11: 01
    Read 12: 00
    Read 13: 00
    Read 14: 00
    Read 15: 00
    Read 16: 00
    Read 17: ff
    Read 18: ff
    Read 19: 04
    Read 20: 78
    Read 21: 78
    Read 22: 04
    Read 23: 78
    Read 24: 78
    Read 25: 06
    Read 26: 00
    Read 27: fe
    Read 28: 00
    Read 29: 00
    Read 30: fe
    Read 31: 00
    Read 32: 00
    Read 33: 00
    Read 34: 00
    Read 35: 00
    Read 36: cc
    Read 37: c0
    Read 38: 00
    Read 39: 00
    Read 40: 00
    Read 41: 50
    Read 42: 00
    Read 43: 80
    Read 44: 80
    Read 45: 00
    Read 46: 00
    Read 47: 00
    Read 48: 00
    Read 49: 00
    Read 50: 00
    Read 51: 04
    Read 52: 00
    Read 53: 00
    Read 54: 00
    Read 55: 00
    Read 56: 00
    Read 57: 00
    Read 58: 04
    Read 59: 00
    Read 60: 00
    Read 61: 00
    Read 62: 00
    Read 63: 00
    Read 64: 00
    Read 65: 04
    Read 66: 00
    Read 67: 00
    Read 68: 00
    Read 69: 00
    Read 70: 00
    Read 71: 00
    Read 72: 04
    Read 73: 00
    Read 74: 00
    Read 75: 00
    Read 76: 00
    Read 77: 00
    Read 78: 00
    Read 79: 00
    Read 80: 00
    Read 81: 00
    Read 82: 00
    Read 83: 00
    Read 84: 00
    Read 85: 00
    Read 86: 08
    Read 87: 00
    Read 88: 00
    Read 89: 00
    Read 90: 00
    Read 91: 00
    Read 92: 00
    Read 93: 08
    Read 94: c0
    Read 95: 00
    Read 96: 00
    Read 97: 00
    Read 98: 00
    Read 99: 00
    Read 100: 00
    Read 101: 01
    Read 102: 00
    Read 103: 00
    Read 104: 00
    Read 105: 00
    Read 106: 00
    Read 107: 00
    Read 108: 00
    Read 109: 00

  • Hello,

    Welcome to E2E and thank you for your interest in our products!

    It is important to consider that when the external clocks are connected to the EVM, the data should be transmitted/received by an external device too. That's why the recording mode sometimes work. So, data should be monitored by the external I2S device.

    Regarding the playback mode, effectively there's a typo error in the datasheet. I have notified this mistake and I'm waiting for the feedback. The bit D0 of Page 0 / Register 93 and 86 should be R/W. So, this bit needs to be written in order to power on the line outputs. The data should be also sent by the external I2S device.

    Please let me know if you have further questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando,

    Thanks for your answer. It is still not OK with the lineout. Anyway this morning I wanted to check the clocks. My target config is I2S in and out, sampling at 96kHz, 24bits, codec using MCLK as clock source and BLCK, WCLK being slave.

    However as an experiment, I feed the I2S master clock externally at 24.576MHz on J14. I set the codec BCLK and WCLK to master and disconnect them from my I2S master device . On the eval main board, SW2 1-3 are ON and 4-8 are OFF. My register settings are pasted below.

    The result is that on the codec board test points I have no BLCK, and WCLK is very much not periodic (expecting 96kHz). Could WCLK still be driven by the TAS1020? Why no BCLK?

    Please indicate your timezone.

    Best regards,

    Jerome

        #reg, value
    
        ## Page zero
        0, 0,
    
        ## Codec Sample Rate
        ## fs(ref)/1 for ADC and DAC
        2, 0, #default
    
        ## PLL reg A
        ## D7=0 PLL disabled
        ## D6-D3=0010 Q=2
        3, 0x10, #default
    
        ## Codec data-path
        ## D7=0 fs(ref) 48kHz
        ## D6-D5=11 ADC and DAC dual rate
        ## D4-D3=01 left DAC enabled
        ## D2-D1=01 right DAC enabled
        ## D0=0 reserved
        7, 0x6A,
    
        ## Serial IF reg A
        ## D7=1 BCLK master
        ## D6=1 WCLK master
        ## D5=0 No TDM
        ## D4=0 Don't care
        ## D3=0 Reserved
        ## D2=0 No 3D
        ## D1-D0=0 reserved
        8, 0xC0,
    
        #### Serial IF reg B
        ## D7-D6=00 I2S
        ## D5-D4=10 24bits
        ## D3=0 don't care
        ## D2=0 what's the use of this (default)
        ## D1=0 what's the use of this (default)
        ## D0=0 don't care
        9, 0x20,
    
        #### Serial IF reg C
        ## Data offset 1
        10, 0x01,
    
        #### Left ADC PGA gain
        ## D7=0 enabled
        ## D6-D0=0000000 0dB (to try)
        15, 0,
    
        #### Right ADC PGA gain
        ## D7=0 enabled
        ## D6-D0=0000000 0dB (to try)
        16, 0,
    
        #### LINE2 to left ADC
        ## D7-D4=0 LINE2L connected to left ADC
        ## D3-D0=F LINE2R not connected
        #17, 0x0F,
    
        #### LINE2 to right ADC
        ## D7-D4=F LINE2L not connected 
        ## D3-D0=0 LINE2R connected to right ADC
        #18, 0xF0,
    
        #### LINE1LP Left ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F LINE1LP not connected
        ## D2=1 left ADC up
        ## D1-D0=00 (default, don't care) 
        #19, 0x7C,
        19, 0x04,
    
        #### LINE1RP to left ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2-D0=0 reserved (default) 
        #21, 0,
    
        #### LINE1RP to right ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2=1 right ADC up
        ## D1-D0=0 (default, don't care) 
        #22, 0x7C,
        22, 0x04,
    
        #### LINE1LP to right ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2-D0=0 reserved (default) 
        #22, 0,
    
        #### DAC power
        ## D7-D6=11 Left and right DACs up
        37, 0xC0,
    
        #### DAC output switching
        ## D7-D6=01 DAC_L3 direct connection of DAC to lineout
        ## D5-D4=01 DAC_R3 direct connection of DAC to lineout
        41, 0x50,
        ## DAC_R1 and DAC_L1
        #41, 0x0,
        ## DAC_R2 and DAC_L2
        #41, 0xC0,
    
        #### Left DAC digital volume
        ## D7=0 unmute
        #43, 0,
    
        #### Right DAC digital volume
        ## D7=0 unmute
        #44, 0,
    
        ## DAC_L1 to LEFT_LOP
        #82, 0x80,
        ## DAC_R1 to RIGHT_LOP
        #92, 0x80,
    
        ## PGA_L to LEFT_LOP
        #81, 0x80,
        ## PGA_R to RIGHT_LOP
        #91, 0x80,
    
        #### LEFT_LOP output level
        ## D7-D4=0000 0dB
        ## D3=1 unmuted
        86, 0x08,
    
        #### RIGHT_LOP output level
        ## D7-D4=0000 0dB
        ## D3=1 unmuted
        93, 0x08,
    
        #### Clock register
        ## D0=1 ext clock
        101, 1,
    
        #### Clock generation
        ## D7-D6=00 CLKDIV_IN uses MCLK (default)
        102, 0, # default
    

  • Hi, Jerome,

    I reviewed your register configuration and it seems that it is configured for 192KHz. The dual rate is being enabled. So, there will be an additional division by 0.5. This makes that sampling rate and WCLK are 24.576MHz / (256*0.5) = 192KHz. So, I would recommend to increase the Q value to 4.

    Once the clock settings are configured correctly and the ADCs/DACs are turned on, you should get a clock output on BCLK and WCLK.

    Additionally, in order to turn on RIGHT_LOP and LEFT_LOP, bit D0 of registers 86 and 93 must be '1'.

    The TAS1020b cannot reach 96KHz. So, it cannot be used in this application.

    My time zone is (UTC-06:00, Dallas Time).

    Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando,

     Thanks for your answer. Setting Q to 4 and also setting 32 bits word length in register 9 got my clocks OK. WCLK is 96kHz and BCLK is 6.14MHz. Now the serial data out is somewhat strange. In the above screenshot you will see the configuration I want to achieve. This is the config screen of my other I2S device, that you see configured as I2S master for clarity. But during my experiments it only outputs MCLK and WCLK, BCLK are generated by the codec. I also monitor the clocks with an oscilloscope.


    So with the scope, I always see the 7 first data bits of a frame to 0. It is just as if the data is always right justified, whatever I set register 9 D7-D6 to. Also the number of high data bits does not look very much affected by the amplitude of the input (visually, at the scope). I input the signal on the J8 connector, with JMP3, JMP4 and JMP10 removed. IN2L and IN2R should be configured as linein with default gains (0dB).

    Could you please confirm the I2S configuration I want to achieve is actually possible? Shouldn't the data be left justified when I set register 9 D7-D6 to 00, and the last 7 data bits of a frame be 0?

    Is there anything wrong with my configuration of IN2L/R?

    Below my registers settings. Only changes are Q=4 and lineout powered on (reg 86, 93).

    What is the timezone of the moderator?

    Best regards,

    Jerome.

        #reg, value

        ## Page zero
        0, 0,

        ## Codec Sample Rate
        ## fs(ref)/1 for ADC and DAC
        2, 0, #default

        ## PLL reg A
        ## D7=0 PLL disabled
        ## D6-D3=0100 Q=4
        3, 0x20,
        ## Q=2
        #3, 0x10, #default

        ## Codec data-path
        ## D7=0 fs(ref) 48kHz
        ## D6-D5=11 ADC and DAC dual rate
        ## D4-D3=01 left DAC enabled
        ## D2-D1=01 right DAC enabled
        ## D0=0 reserved
        7, 0x6A,

        ## Serial IF reg A
        ## D7=1 BCLK master
        ## D6=1 WCLK master
        ## D5=0 No TDM
        ## D4=0 Don't care
        ## D3=0 Reserved
        ## D2=0 No 3D
        ## D1-D0=0 reserved
        8, 0xC0,

        #### Serial IF reg B
        ## D7-D6=00 I2S
        ## D5-D4=11 32bits
        ## D3=0 continuous mode (not 256 BCLK per WCLK)
        ## D2=0 what's the use of this (default)
        ## D1=0 what's the use of this (default)
        ## D0=0 don't care
        9, 0x30,
        ## Left justified data
        #9, 0xF0,
        ## Right justified data
        #9, 0xB0,

        #### Serial IF reg C
        ## Data offset 1
        #10, 0x01,
        ## Data offset 0
        10, 0x00,

        #### Left ADC PGA gain
        ## D7=0 enabled
        ## D6-D0=0000000 0dB (to try)
        15, 0,

        #### Right ADC PGA gain
        ## D7=0 enabled
        ## D6-D0=0000000 0dB (to try)
        16, 0,

        #### LINE2 to left ADC
        ## D7-D4=0 LINE2L connected to left ADC
        ## D3-D0=F LINE2R not connected
        #17, 0x0F,

        #### LINE2 to right ADC
        ## D7-D4=F LINE2L not connected
        ## D3-D0=0 LINE2R connected to right ADC
        #18, 0xF0,

        #### LINE1LP Left ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F LINE1LP not connected
        ## D2=1 left ADC up
        ## D1-D0=00 (default, don't care)
        #19, 0x7C,
        19, 0x04,

        #### LINE1RP to left ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2-D0=0 reserved (default)
        #21, 0,

        #### LINE1RP to right ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2=1 right ADC up
        ## D1-D0=0 (default, don't care)
        #22, 0x7C,
        22, 0x04,

        #### LINE1LP to right ADC control
        ## D7=0 single-ended (default)
        ## D6-D3=F not connected
        ## D2-D0=0 reserved (default)
        #22, 0,

        #### DAC power
        ## D7-D6=11 Left and right DACs up
        37, 0xC0,

        #### DAC output switching
        ## D7-D6=01 DAC_L3 direct connection of DAC to lineout
        ## D5-D4=01 DAC_R3 direct connection of DAC to lineout
        41, 0x50,
        ## DAC_R1 and DAC_L1
        #41, 0x0,
        ## DAC_R2 and DAC_L2
        #41, 0xC0,

        #### Left DAC digital volume
        ## D7=0 unmute
        #43, 0,

        #### Right DAC digital volume
        ## D7=0 unmute
        #44, 0,

        ## DAC_L1 to LEFT_LOP
        #82, 0x80,
        ## DAC_R1 to RIGHT_LOP
        #92, 0x80,

        ## PGA_L to LEFT_LOP
        #81, 0x80,
        ## PGA_R to RIGHT_LOP
        #91, 0x80,

        #### LEFT_LOP output level
        ## D7-D4=0000 0dB
        ## D3=1 unmuted
        86, 0x09,

        #### RIGHT_LOP output level
        ## D7-D4=0000 0dB
        ## D3=1 unmuted
        93, 0x09,

        #### Clock register
        ## D0=1 ext clock
        101, 1,

        #### Clock generation
        ## D7-D6=00 CLKDIV_IN uses MCLK (default)
        102, 0, # default

  • Hi, Jerome,

    Effectively, you should get first the MSB bits since the clocks are configured for 32-bits and I2S. I noticed that IN2 code lines seem to be commented (#17, 0x0F,). Could you try disabling the IN1 input lines (just leaving the ADC powered on with registers 19 and 22) and omitting the comments on IN2 code lines?

    This will ensure that the sent data will be related only with IN2 lines.

    Thank you.




    Olivier,

    Could you comment about your timezone?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Jose Fernando,

    OMG, no wonder my MSB's were 0. Sorry for that.
    OK now ADC and DAC are working well enough to go on. One last thing (for now) that worries me. I write 0x9 to regs 86 and 93 as we said, but they read back as 0xb, D1 set meaning "Not all programmed gains to LEFT_LOP/M have been applied yet". Should I care about that?

    Also, this morning I took the second EVM Olivier sent me, checked the jumpers and connected the GUI. Well the GUI does work! It was just completely unexpected to me I had to playback and record on the PC.

    As for the timezone: the moderator and the expert being in different timezones can cause losing a day.

    Thanks again,
    Jerome.
  • Hi, Jerome,

    I'm glad to read that it worked correctly.

    Regarding your question about the D1 bit of registers 86 and 93, you need to ensure that all the volume blocks from DAC to the line output are enabled and un-muted. Once they are enabled and un-muted, the register should show that all the gains are applied correctly at the line output.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Jose Fernando,

    We have hooked the TLV320AIC3104EVM board to one of our prototype, without the carrier (modem) board. So basically, power, I2C and I2S are fed by one of our board. Register settings for the codec are the same as those used during the evaluation, except register 3 (Q=2).
    I2C comm works fine.
    I2S lines look good: MCLK at 12.x MHz, BCLK at 6.x MHz, WCLK at 96kHz. DIN and DOUT look good too (played 1's, 0's, -1's). Data is sampled on rising edge of BCLK. I2S config has not changed on our board, which worked with another codec beforehand.

    Recording works. Playback does not work. It is very weird: it just looks like the lineout is very very slow to react. I can play 1's or -1's: but the level is very slow to appear on the lineout. When playing a 440Hz sine, the output is a 2.x Hz sine !!!?

    I am open to ANY suggestion :)

    Is it problem BCLK is off when programming the codec? (MCLK is on of course).
    Lineout is not connected and output is measured at LEFT+, RIGHT+ pads on the board.

    Below the log of the codec registers programming (sorry regs in hex):

    Tomorrow is off, I am back on monday.

    Best regards;
    Jerome.

    root@paros:/testUS # ./aic3104.sh
    writing 0x18-0x0: 0x0
    reading 0x18-0x0: 0x00
    writing 0x18-0x1: 0x80
    reading 0x18-0x1: 0x00
    writing 0x18-0x2: 0x0
    reading 0x18-0x2: 0x00
    writing 0x18-0x3: 0x10
    reading 0x18-0x3: 0x10
    writing 0x18-0x7: 0x6a
    reading 0x18-0x7: 0x6a
    writing 0x18-0x8: 0x0
    reading 0x18-0x8: 0x00
    writing 0x18-0x9: 0x30
    reading 0x18-0x9: 0x30
    writing 0x18-0xa: 0x0
    reading 0x18-0xa: 0x00
    writing 0x18-0xf: 0x0
    reading 0x18-0xf: 0x00
    writing 0x18-0x10: 0x0
    reading 0x18-0x10: 0x00
    writing 0x18-0x11: 0xf
    reading 0x18-0x11: 0x0f
    writing 0x18-0x12: 0xf0
    reading 0x18-0x12: 0xf0
    writing 0x18-0x13: 0x7c
    reading 0x18-0x13: 0x7c
    writing 0x18-0x16: 0x7c
    reading 0x18-0x16: 0x7c
    writing 0x18-0x25: 0xc0
    reading 0x18-0x25: 0xc0
    writing 0x18-0x29: 0x50
    reading 0x18-0x29: 0x50
    writing 0x18-0x2b: 0x0
    reading 0x18-0x2b: 0x00
    writing 0x18-0x2c: 0x0
    reading 0x18-0x2c: 0x00
    writing 0x18-0x56: 0x9
    reading 0x18-0x56: 0x0b
    writing 0x18-0x5d: 0x9
    reading 0x18-0x5d: 0x0b
    writing 0x18-0x65: 0x1
    reading 0x18-0x65: 0x01
    writing 0x18-0x66: 0x2
    reading 0x18-0x66: 0x02
    reading 0x18-0xb: 0x41
    Should be: 0x01
    reading 0x18-0x20: 0x00
    Should be: 0
    reading 0x18-0x21: 0x00
    Should be: 0
    reading 0x18-0x24: 0x44
    Should be: 0xCC
    reading 0x18-0x56: 0x0b
    Should be: 0x09
    reading 0x18-0x5d: 0x0b
    Should be: 0x09
    reading 0x18-0x5e: 0xd8
    Should be: 0xD8
    reading 0x18-0x5f: 0x00
    Should be: 0
    reading 0x18-0x60: 0x00
    Should be: 0
    reading 0x18-0x61: 0x00
    Should be: 0
  • Hi, Jerome,

    It seems to be related with a clock issue. I recommend to ensure that all the clocks are enabled before the I2C writing sequence. The ADCs and DACs need of several BCLK pulses to get initialized correctly.

    Additionally, ensure that the sampling rate has the same value than the WCLK.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando, TI people,

    Still can't make the codec work with MCLK=12.2880MHz. This fails with two master devices: an Audio Precision and our proto board.

    Please try that on your side because I strongly believe the codec cannot do what it is asked to do.

    Codec is slave for all clocks.
    MCLK is set to 12.2880MHz
    WCLK is set to 96kHz
    Data with is 32 bits

    BCLK is measured at 6.14MHz

    Q is set to 2
    Dual rate is enabled

    With this configuration, recording works fine on all the bandwidth, but playback completely fails, on all the bandwidth.

    I have been able to have the codec fully working with MCLK at 24.5760MHz (same config, but with Q=4). So please check that the requested configuration with MCLK at 12.2880MHz is actually possible.

    Below my register settings.

    Best regards,
    Jerome.

    #reg, value

    ## Page zero
    0, 0,

    ## Codec Sample Rate
    ## fs(ref)/1 for ADC and DAC
    2, 0, #default

    ## PLL reg A
    ## D7=0 PLL disabled
    ## D6-D3=0010 Q=2
    3, 0x10,

    ## Codec data-path
    ## D7=0 fs(ref) 48kHz
    ## D6-D5=11 ADC and DAC dual rate
    ## D4-D3=01 left DAC enabled
    ## D2-D1=01 right DAC enabled
    ## D0=0 reserved
    7, 0x6A,

    ## Serial IF reg A
    ## D7=0 BCLK slave
    ## D6=0 WCLK slave
    ## D5=0 No TDM
    ## D4=0 Don't care
    ## D3=0 Reserved
    ## D2=0 No 3D
    ## D1-D0=0 reserved
    8, 0, #default

    #### Serial IF reg B
    ## D7-D6=00 I2S
    ## D5-D4=11 32bits
    ## D3=0 continuous mode (not 256 BCLK per WCLK)
    ## D2=0 what's the use of this (default)
    ## D1=0 what's the use of this (default)
    ## D0=0 don't care
    9, 0x30,
    ## Left justified data
    #9, 0xF0,
    ## Right justified data
    #9, 0xB0,

    #### Serial IF reg C
    ## Data offset 1
    #10, 0x01,
    ## Data offset 0
    10, 0x00,

    #### Left ADC PGA gain
    ## D7=0 enabled
    ## D6-D0=0000000 0dB (to try)
    15, 0,

    #### Right ADC PGA gain
    ## D7=0 enabled
    ## D6-D0=0000000 0dB (to try)
    16, 0,

    #### LINE2 to left ADC
    ## D7-D4=0 LINE2L connected to left ADC
    ## D3-D0=F LINE2R not connected
    17, 0x0F,

    #### LINE2 to right ADC
    ## D7-D4=F LINE2L not connected
    ## D3-D0=0 LINE2R connected to right ADC
    18, 0xF0,

    #### LINE1LP Left ADC control
    ## D7=0 single-ended (default)
    ## D6-D3=F LINE1LP not connected
    ## D2=1 left ADC up
    ## D1-D0=00 (default, don't care)
    19, 0x7C,
    #19, 0x04,

    #### LINE1RP to left ADC control
    ## D7=0 single-ended (default)
    ## D6-D3=F not connected
    ## D2-D0=0 reserved (default)
    #21, 0,

    #### LINE1RP to right ADC control
    ## D7=0 single-ended (default)
    ## D6-D3=F not connected
    ## D2=1 right ADC up
    ## D1-D0=0 (default, don't care)
    22, 0x7C,
    #22, 0x04,

    #### LINE1LP to right ADC control
    ## D7=0 single-ended (default)
    ## D6-D3=F not connected
    ## D2-D0=0 reserved (default)
    #22, 0,

    #### DAC power
    ## D7-D6=11 Left and right DACs up
    37, 0xC0,

    #### DAC output switching
    ## D7-D6=01 DAC_L3 direct connection of DAC to lineout
    ## D5-D4=01 DAC_R3 direct connection of DAC to lineout
    41, 0x50,
    ## DAC_R1 and DAC_L1
    #41, 0x0,
    ## DAC_R2 and DAC_L2
    #41, 0xC0,

    #### Left DAC digital volume
    ## D7=0 unmute
    43, 0,

    #### Right DAC digital volume
    ## D7=0 unmute
    44, 0,

    ## DAC_L1 to LEFT_LOP
    #82, 0x80,
    ## DAC_R1 to RIGHT_LOP
    #92, 0x80,

    ## PGA_L to LEFT_LOP
    #81, 0x80,
    ## PGA_R to RIGHT_LOP
    #91, 0x80,

    #### LEFT_LOP output level
    ## D7-D4=0000 0dB
    ## D3=1 unmuted
    86, 0x09,

    #### RIGHT_LOP output level
    ## D7-D4=0000 0dB
    ## D3=1 unmuted
    93, 0x09,

    #### Clock register
    ## D0=1 ext clock
    101, 1,

    #### Clock generation
    ## D7-D6=00 CLKDIV_IN uses MCLK (default)
    102, 2, # default

    #109: try hight current mode
  • Hi, Jerome,

    I found this E2E thread that could be useful for your application. I think that this issue is related with the Q value:

    e2e.ti.com/.../147640

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando,

    OK now that works and schematic is almost ready. Thanks for your support.

    One last detail: we are using LINE1 in differential mode. LINE1LP goes to left ADC andLINE1RP goes to right ADC. So for example with LINE1L, do I have to set the differential bit in both registers 19 and 24, or should I only program register 19 and leave 24 at its reset value?


    Best regards,

    Jerome.

  • Hi, Jerome,

    As mentioned in the Table 25 and 30, both registers must be set with the same configuration (single-ended or fully-differential mode). So, please configure bit D7 as '1' on both registers to use the differential mode.

    Best regards,
    Luis Fernando Rodríguez S.