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TLV320ADC3101: ADC3101 configuration for Master mode

selvam mk
Intellectual 970 points
Part Number: TLV320ADC3101

Hi All,

We are using the ADC3101 device in master mode.

Mclk with external crystal = 19.2Mhz and we want to capture the data with sampling rate of 8Khz, 44.1Khz and 48Khz.

Configured page 0/Register 27 to 0x0C, and how to get 256Khz bclk and 8Khz wclk?

Regards,

Manoj

  • 0
    TI__Guru 57800 points

    Hi, Selvam,

    In order to configure this device to provide the correct clocks in master mode from a 19.2MHz MCLK, some considerations should be made. As the frequency of the MCLK signal is not a typical audio clock (like 12.288MHz), you need to use the PLL and dividers of the ADC to generate the correct clock outputs. 

    Please refer to below codes for the clock configurations you are requesting. 32×Fs BCLK is considered for the configuration.

    Fs = 8 kHz:

    # Clock Settings
#  IN:  MCLK = 19.2 MHz
#  OUT: BLCK = 256 kHz, WCLK = 8 kHz

# Select Page 0
w 30 00 00
# Dividers ON, NADC = 3, MADC = 32
w 30 12 83 A0
# AOSR = 128 (default)
w 30 14 80
# BDIV_CLKIN ON, N=128
w 30 1E 80
# PLL J=5
w 30 06 05
# PLL D=1200
w 30 07 04 B0
# PLL_CLKIN = MCLK, CODEC_CLKIN = PLL_CLK
w 30 04 03
# PLL ON, P = 1, R = 1
w 30 05 91

    Fs = 44.1 kHz:

    # Clock Settings
#  IN:  MCLK = 19.2 MHz
#  OUT: BLCK = 1.411 MHz, WCLK = 44.1 kHz

# Select Page 0
w 30 00 00
# Dividers ON, NADC = 8, MADC = 2
w 30 12 88 82
# AOSR = 128 (default)
w 30 14 80
# BDIV_CLKIN ON, N=8
w 30 1E 88
# PLL J=4
w 30 06 04
# PLL D=7040
w 30 07 1B 80
# PLL_CLKIN = MCLK, CODEC_CLKIN = PLL_CLK
w 30 04 03
# PLL ON, P = 1, R = 1
w 30 05 91

    Fs = 48 kHz:

    # Clock Settings
#  IN:  MCLK = 19.2 MHz
#  OUT: BLCK = 1.536 MHz, WCLK = 48 kHz

# Select Page 0
w 30 00 00
# Dividers ON, NADC = 8, MADC = 2
w 30 12 88 82
# AOSR = 128 (default)
w 30 14 80
# BDIV_CLKIN ON, N=8
w 30 1E 88
# PLL J=5
w 30 06 05
# PLL D=7040
w 30 07 04 B0
# PLL_CLKIN = MCLK, CODEC_CLKIN = PLL_CLK
w 30 04 03
# PLL ON, P = 1, R = 1
w 30 05 91

    Best Regards,

      -Diego Meléndez López
        Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Intellectual 970 points
    Hi Diego,

    With above settings (example 44.1Khz) settings in Master mode Out clocks differs.

    We are getting Wclk = 37Khz and Bclk =1.2Mhz, which register we need to change to adjust the value?

    If I want to capture mono channel, how to change this settings?

    Regards,
    Mk
  • 0 in reply to selvam mk
    TI__Guru 57800 points

    Hi, Selvam,

    Thanks for the feedback. I have verified above settings with an EVM and the sampling rates obtained are correct when using a master clock of 19.2MHz. Could you please double check the master clock frequency used?. 

    About the mono channel capture, it is possible to configure any of the inputs of the device through the mixers into left or right ADCs. As example, if a mono signal is being provided to IN1L(P), you can simply route this signal to both left and right ADCs by writing the following code:

    #Select Page 1
    w 30 00 01
# IN1L(P) connected to Left ADC, 0-dB setting
    w 30 34 FC
    #IN1L(P) connected to Right ADC, 0-dB setting
w 30 39 3C

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Intellectual 970 points

    Hi Diego,

    Yes we are using 19.2Mhz clock. Any other factor which can reduce the clock?

    we are using IN2R(P) which is going only to Right ADC, I did't see IN2R(P) can go to Left ADC

    Regards,

    Mk

  • 0 in reply to selvam mk
    Intellectual 970 points

    selvam mk said:
    Yes we are using 19.2Mhz clock. Any other factor which can reduce the clock?

    Now I could get correct clock value, issue is with incorrect D value in code.

    Thanks,

  • 0 in reply to selvam mk
    TI__Guru 57800 points

    Hi, Selvam,

    Thanks for the feedback, glad to hear the clocks are now generated properly. 

    Regarding your question on the routing, IN2R(P) can only be routed to the right ADC as a single-ended input. In order to stream the same signal to both left and right ADCs, you need to use a different input like IN1L(P).

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Intellectual 970 points

    Hi Diego,

    Now we are capturing audio with 44.1khz setting(with 1-2m distance), without AGC capture volume is audible  with some noise. If we enable right AGC capture volume is reduced to low.

    How to get the better capture volume with AGC?

    Settings used are:

    AGC Noise Threshold -90db
    AGC Target Level -14db
    AGC Max PGA Gain 35db
    analog pga gain 35db

    Regards,

    Manoj