What is the max jitter specification required on SCK3 in order to meet the specified SNR (say -125dB @ 17kHz)?
For example, with a 48kHZ sample clock (SCLK3 = 18.432MHz, 384Fs) and an output frequency we calculate the jitter needed for ~ 125dB SNR as:
SNR_jitter = 20 * Log(2*pi*17kHz*T_jitter)
T_jitter = 5 psec for -125dB SNR
The datasheet suggests using a PLL1700E for the clock source but it has a jitter of ~ 150psec which is much larger that the theoretical need of 5psec. The datasheet mentions tolerance to clock jitter but this is not well described.
