Other Parts Discussed in Thread: CC2640R2F, , TPS799, , TLV320AIC3256
I have been working with the a tas2505 connected to a cc2640r2f. I have configured the devices with a bclock of 1.92Mhz and a wclk of 48Khz. I have the Hp powered down. I have PTM_P2 selected. I am driving the dac with 19-20kHz tones. Configuration file is attached.
The tas2505 is configured with the internal LDO powering AVDD and DVDD. SPKVDD and IOVDD are connected to 3.0V. I have disconnected the Speaker and HP outputs for testing internal current draw.
I get a reading of 47ma. based off of the tables in section 2.5.2.1 and 2.5.3.1 of the TAS2505 Application Reference Guide, I would expect the current consumption to be about 18mA (plus PLL current). I have tried re-configuring the tas2505 and cc2640r2f so the pll is disabled, but it only reduces the current to 46 mA. As 18mA is pushing my power budget already, does anyone know what I am doing wrong, or can you recommend a lower power DAC/amplifier for the job?
audioCodec_reset(); // based off of example script in TAS2505 Application Reference Guide SLAU472 // # I2C Script to Setup the device in Playback Mode // # Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY // # This script set DAC output routed to HP Driver and Class-D driver via Mixer // # # ==> comment delimiter //======= // Reset //======= // # Page switch to Page 0 // W 30 00 00 audioCodec_pageSelect(AUDIO_CODEC_PAGE_0); // # Assert Software reset (P0, R1, D0=1) // W 30 01 01 audioCodec_regWrite(AUDIO_CODEC_SW_RESET_REG, 0x01); //====== // Power //====== // # Page Switch to Page 1 // W 30 00 01 audioCodec_pageSelect(AUDIO_CODEC_PAGE_1); // # LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0) // W 30 02 00 audioCodec_regWrite(AUDIO_CODEC_LDO_CTRL_REG, 0x00); //===== // PLL //===== // # Page switch to Page 0 // W 30 00 00 audioCodec_pageSelect(AUDIO_CODEC_PAGE_0); #if 1 // # PLL_clkin = MCLK, codec_clkin = PLL_CLK, MCLK should be 11.2896MHz (P0, R4, D1-D0=03) // w 30 04 03 // different, we use bclk @ 1.92MHz PLL_clkin = BCLK, codec_clkin = PLL_CLK audioCodec_regWrite(AUDIO_CODEC_CLK_MUX_REG, 0x07); // # Power up PLL, set P=1, R=1, (Page-0, Reg-5) // w 30 05 91 // # Set J=4, (Page-0, Reg-6) // w 30 06 04 // # D = 0000, D(13:8) = 0, (Page-0, Reg-7) // w 30 07 00 // # D(7:0) = 0, (Page-0, Reg-8) // w 30 08 00 // we have different clocks (input 11.2896Mhz/44.1Khz vs 1.92Mhz/48Khz) audioCodec_regWrite(AUDIO_CODEC_CLK_PLL_P_R_REG, 0x11 | 0x80);// PLL is powered up, P=1, R=1 audioCodec_regWrite(AUDIO_CODEC_CLK_PLL_J_REG, 48); // J=48 audioCodec_regWrite(AUDIO_CODEC_CLK_PLL_D_MSB_REG, 0x00); // D = 0 audioCodec_regWrite(AUDIO_CODEC_CLK_PLL_D_LSB_REG, 0); // D = 0 #if 1 // # add delay of 15 ms for PLL to lock // d 15 Task_sleep(15 * 1000 / Clock_tickPeriod); #endif //=============== // clock dividers //=============== // # DAC NDAC Powered up, NDAC=4 (P0, R11, D7=1, D6-D0=0000100) // W 30 0B 84 // # DAC MDAC Powered up, MDAC=2 (P0, R12, D7=1, D6-D0=0000010) // W 30 0C 82 // # DAC OSR(9:0)-> DOSR=128 (P0, R12, D1-D0=00) // W 30 0D 00 // # DAC OSR(9:0)-> DOSR=128 (P0, R13, D7-D0=10000000) // W 30 0E 80 // again, we have different clocks. // we use a 1.92 Mhz Bclk as the source clock for the PLL and // our sample clock is 48KHz audioCodec_regWrite(AUDIO_CODEC_CLK_NDAC_REG, 3 | 0x80); //NDAC divider powered up, NDAC = 3; audioCodec_regWrite(AUDIO_CODEC_CLK_MDAC_REG, 5 | 0x80); // MDAC divider powered up, MDAC = 5; audioCodec_regWrite(AUDIO_CODEC_DAC_OSR_MSB_REG, 0x00); // DOSR = 128 audioCodec_regWrite(AUDIO_CODEC_DAC_OSR_LSB_REG, 128); // DOSR = 128 #else audioCodec_regWrite(AUDIO_CODEC_CLK_MUX_REG, 0x01); audioCodec_regWrite(AUDIO_CODEC_CLK_NDAC_REG, 1 | 0x80); //NDAC divider powered up, NDAC = 1; audioCodec_regWrite(AUDIO_CODEC_CLK_MDAC_REG, 5 | 0x80); // MDAC divider powered up, MDAC = 5; audioCodec_regWrite(AUDIO_CODEC_DAC_OSR_MSB_REG, 0x00); // DOSR = 100 audioCodec_regWrite(AUDIO_CODEC_DAC_OSR_LSB_REG, 100); // DOSR = 100 #endif //============= // Word format //============= // # Codec Interface control Word length = 16bits, BCLK&WCLK inputs, I2S mode. (P0, R27, D7- // D6=00, D5-D4=00, D3-D2=00) // W 30 1B 00 audioCodec_regWrite(AUDIO_CODEC_AUDIO_IF_1_REG, 0x00); // 0x00 16bit, I2S, BCLK is input to the device // # Data slot offset 00 (P0, R28, D7-D0=0000) // W 30 1C 00 audioCodec_regWrite(AUDIO_CODEC_AUDIO_IF_2_REG_DATA_OFFSET, 0x00); //============ // DSP Config //============ // # Dac Instruction programming PRB #2 for Mono routing. Type interpolation (x8) and 3 programmable // Biquads. (P0, R60, D4-D0=0010) // W 30 3C 02 audioCodec_regWrite(AUDIO_CODEC_DAC_SIG_P_BLK_CTRL_REG, 0x02); //======================= // DSP biquad coeffients //======================= #if 1 // msw todo we should keep this generic and move this filter to the // tha aud source code // add biquad filter //##########--------------- BEGIN COEFFICIENTS -------------------------------------- //# reg 00 - Page Select Register = 44 //# sets active page to page 44 for 3-BQs (BQ-A, BQ-B, BQ-C) //w 30 00 2C audioCodec_pageSelect(AUDIO_CODEC_PAGE_44); // //----------------------------------------------------------------------- // BQ-A = 19500 Hz Bandpass BW = 5000 Hz // Calculated using purepath studio and verified against http://engineerjs.com //----------------------------------------------------------------------- // note: coefficients are big endian // Filter Coefficient Mono DAC Channel // Biquad A N0 C1 (Page 44, registers 12, 13, 14) // N1 C2 (Page 44, registers 16, 17, 18) // N2 C3 (Page 44, registers 20, 21, 22) // D1 C4 (Page 44, registers 24, 25, 26) // D2 C5 (Page 44, registers 28, 29, 30) // reg 12/13/14 - N0 Coefficient = 0.25342714786529541015625 = 0x20704D audioCodec_regWrite(12, 0x20); audioCodec_regWrite(13, 0x70); audioCodec_regWrite(14, 0x4D); // reg 16/17/18 - N1 Coefficient = 0 (note: this is 1/2 of conventional N1) audioCodec_regWrite(16, 0x00); audioCodec_regWrite(17, 0x00); audioCodec_regWrite(18, 0x00); //reg 20/21/22 - N2 Coefficient = -0.25342714786529541015625 = 0xDF8FB3 audioCodec_regWrite(20, 0xdf); audioCodec_regWrite(21, 0x8f); audioCodec_regWrite(22, 0xb3); // reg 24/25/26 - D1 Coefficient = -0.655541896820068359375 = 0xAC1734 // Note this is negative 1/2 of conventional D1 audioCodec_regWrite(24, 0xac); audioCodec_regWrite(25, 0x17); audioCodec_regWrite(26, 0x34); // reg 28/29/30 - D2 Coefficient = -0.49314534664154052734375 = 0xC0E09D // note this is negative of conventional D2 audioCodec_regWrite(28, 0xc0); audioCodec_regWrite(29, 0xe0); audioCodec_regWrite(30, 0x9d); #else // add biquad filter //##########--------------- BEGIN COEFFICIENTS -------------------------------------- //# reg 00 - Page Select Register = 44 //# sets active page to page 44 for 3-BQs (BQ-A, BQ-B, BQ-C) //w 30 00 2C audioCodec_pageSelect(AUDIO_CODEC_PAGE_44); // // All pass filter // // note: coefficients are big endian // Filter Coefficient Mono DAC Channel // Biquad A N0 C1 (Page 44, registers 12, 13, 14) // N1 C2 (Page 44, registers 16, 17, 18) // N2 C3 (Page 44, registers 20, 21, 22) // D1 C4 (Page 44, registers 24, 25, 26) // D2 C5 (Page 44, registers 28, 29, 30) audioCodec_regWrite(12, 0x7f); audioCodec_regWrite(13, 0xff); audioCodec_regWrite(14, 0xff); audioCodec_regWrite(16, 0x00); audioCodec_regWrite(17, 0x00); audioCodec_regWrite(18, 0x00); audioCodec_regWrite(20, 0); audioCodec_regWrite(21, 0); audioCodec_regWrite(22, 0); audioCodec_regWrite(24, 0); audioCodec_regWrite(25, 0); audioCodec_regWrite(26, 0); audioCodec_regWrite(28, 0); audioCodec_regWrite(29, 0); audioCodec_regWrite(30, 0); #endif // # Page Switch to Page 1 // W 30 00 01 audioCodec_pageSelect(AUDIO_CODEC_PAGE_1); // # Master Reference Powered on (P1, R1, D4=1) // W 30 01 10 audioCodec_regWrite(AUDIO_CODEC_REF_POR_LDO_BGAP_CTRL_REG, 0x00); // # Output common mode for DAC set to 0.9V (default) (P1, R10) // W 30 0A 00 audioCodec_regWrite(AUDIO_CODEC_COMMON_MODE_CTRL_REG, 0x00); #if 0 // # Mixer P output is connected to HP Out Mixer (P1, R12, D2=1) // w 30 0C 04 // # HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000) // W 30 16 00 // # No need to enable Mixer M and Mixer P, AINL Voulme, 0dB Gain (P1, R24, D7=1, D6-D0=0000000) // W 30 18 00 // # Power up HP (P1, R9, D5=1) // w 30 09 20 // # Unmute HP with 0dB gain (P1, R16, D4=1) // w 30 10 00 #else // mute headphone with - audioCodec_regWrite(AUDIO_CODEC_HPL_DRV_GAIN_CTRL_REG, 0x40); // power headphone down audioCodec_regWrite(AUDIO_CODEC_OP_DRV_PWR_CTRL_REG, 0x00); #endif audioCodec_regWrite(AUDIO_CODEC_PLAYBACK_CFG_REG, 0x08); // # SPK attn. Gain =0dB (P1, R46, D6-D0=000000) // W 30 2E 00 audioCodec_regWrite(AUDIO_CODEC_SPKR_AMP_VOL_CTRL_1_REG, 0x00); // # SPK driver Gain=6.0dB (P1, R48, D6-D4=001) // W 30 30 10 audioCodec_regWrite(AUDIO_CODEC_SPKR_AMP_VOL_CTRL_2_REG, 0x10); // # SPK powered up (P1, R45, D1=1) // W 30 2D 02 audioCodec_regWrite(AUDIO_CODEC_SPKR_AMP_CTRL_1_REG, 0x02); // # Page switch to Page 0 // W 30 00 00 audioCodec_pageSelect(AUDIO_CODEC_PAGE_0); // # DAC powered up, Soft step 1 per Fs. (P0, R63, D7=1, D5-D4=01, D3-D2=00, D1-D0=00) // W 30 3F 90 audioCodec_regWrite(AUDIO_CODEC_DAC_CHANNEL_SETUP_1_REG, 0x90); // # DAC digital gain 0dB (P0, R65, D7-D0=00000000) // W 30 41 00 audioCodec_regWrite(AUDIO_CODEC_LEFT_DAC_VOL_CTRL_REG, 0x00); //# DAC volume not muted. (P0, R64, D3=0, D2=1) // W 30 40 04 audioCodec_regWrite(AUDIO_CODEC_DAC_CHANNEL_SETUP_2_REG, 0x04);