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  • TI Thinks Resolved

PCM5102A: decoupling 3.3 V power supply terminals

Intellectual 965 points

Replies: 19

Views: 2138

Part Number: PCM5102A

Hello,

Having issue with your Application and Implementation on page 26 of the datasheet with part number PCM5102APWR.

Here is the flow:

[ PCM2706CPJTR] > i2s > [PCM5102APWR] > {AMP OUT}

THAT is PCM2706C USB to PCM5102A DAC  to Amplifier Speaker.

I have it setup for PCM5102a PLL Operation 3.3v on a breadboard, clean 3.3v power supply.

Also the XSMT PIN 17 wired to AVDD PIN 8 on the 'Breadboard', per the TI datasheet recommendations. THIS IS THE ONLY DEVIATION.

I have swap out the PCM5102A DAC with another DAC,the ES9023, and the setup works fine!

HOWEVER the TI PCM5102A IC is module not working. I have replace the IC Module with another PCM5102A chip, but same result.

QUESTION:

1. Where do I wire XSMT PIN 17, to AVDD and or DVDD!

2. What is the I2S hardware configuration for optimal high-resolution performance!

3. What is the best TI I2S hardware configuration recommended!

Note I have review the wiring to your Application and Implementation on page 26 of the datasheet to my breadboard wiring using the same BOM and wiring. Not getting any signal output!

I have replace the IC since we have several PCM5102 IC module made up for bread-boarding.

Regards

  • In reply to Neil Henry:

    Kindly see the schematic for reference, thank you.
  • In reply to Neil Henry:

    Hi Neil,

    Breadboarding complex configurations can be problematic as simple errors may not be easily detected.  Firstly, I would confirm that all of the required additional circuitry is connected correctly, specifically charge pump cap between CAPM and CAPP, the stability capacitors on LDOO and VNEG, as well as the state of the configuration pins (FMT, FLT, and DEMP).  Assuming those are correct, and XSMT is tied high (note muted) by being connected to any 3.3V supply, we should confirm that the I2S data is valid.  If FMT is grounded, the device is expecting standard I2S data.

    Note that in 3-wire mode, only a select number of rates are allowed.  Table 11 lists these.

    In addition, if you are using 3 wire mode on a breadboard, I recommend you GND SCK to ensure that now digital feedthrough on the board is causing the PLL auto-detect to think there is a clock on the line.

    I think checking these configurations should fix the issues.

    Thanks!

    Paul

  • In reply to Paul_Frost:

    Hello,

    I have double check the wiring to the TI design and wiring to our breadboard, and have same.

    I followed the outline direction and set all wiring to follow the guided direction.

    However not getting the I2S signal out!

    Note I swap out the PCM5102A with another DAC; and it and works!

    However the PCM5102A has no I2S SIGNAL!

    Not sure what else to check!!! 

    ....Just pop the IC add another, same....no signal out.

    Neil Henry

  • In reply to Neil Henry:

    What is the frequency of the I2S sample rate and bit clock frequency you are using? Can you confirm the voltage on VNEG and LDOO when the I2S signal is being applied?
  • In reply to Paul_Frost:

    Hello Paul,

    We are using the PCM2706C USB I2S on the input. It had has bit clock frequency of 12MHZ and the I2S sample rate is 48KHZ. We are confirming the voltage on VNEG and LDOO.

    What must be the voltage on VNEG and LDOO when the I2S signal is being applied?

    We have supply at 3.3v AVDD, CPVDD, and DVDD.

    Our QC Engineers ask, "How can we know if the IC is operable before assembly on the circuit board i.e. breadboard?"

    What is the TI Quality Control procedure for the IC? They want to test the TI IC prior to production, need your help here, thanks.

    Best Regards,

    Neil Henry

  • In reply to Neil Henry:

    If the I2S signal is valid the device should enable the low power LDO (LDOO) which should measure 1.8V, and the charge pump (VNEG) which should be -3.3V.

    These components are all tested before being sold through our distributors.
  • In reply to Paul_Frost:

    Paul,

    Thanks for the update.

    BASELINE:
    BEFORE I2S Signal Test:

    CPVDD = +3.55V
    DVDD = +3.42V
    AVDD = +3.10V
    LDOO = +3.42V
    VNEG = +3.25V

    BASELINE:
    AFTER/DURING I2S Signal Test APPLIED:

    LDOO = 0.35V [I2S signal applied]
    VNEG = 0.38V

    These measurements don't add up.

    Not sure what this means! Before shows +3.5V but during I2S signal test it goes to 0.35v. SOS!

    Neil Henry
  • In reply to Neil Henry:

    Hi Neil,

    Please verify that you have nothing connected to the LDOO pin besides the capacitor - this is an LDO output, not input. Also verify that nothing is connected to VNEG except the capacitor. I would also meticulously verify the ground pins are connected.
  • In reply to Paul_Frost:

    Hi Paul,

    Our lead engineer has verified that nothing is connected to LDOO and VNEG besides the suggested capacitor per the datasheet schematic.

    Another engineer took on the project, and wired it on a new breadboard with all new parts and IC.

    However not getting I2S signal to PCM5102A DAC.

    FLOW:  USB TI PCM2706C <> I2S <> DAC TI PCM5102A <> AMP <> SPEAKER

    WE  test the flow {USB PCM2706C <> I2S <> DAC ESS ES9023P <> AMP <> SPEAKER} this works GREAT.

    However our project goal is to use the chipset - PCM5102A.

    Not sure what else to do....just baffled!

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