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TLV320AIC3101: pop noise depends on power up sequence

KANJI SHIBATANI
Mastermind 6205 points
Part Number: TLV320AIC3101


Hello

My customer is using  TLV320AIC3101 for several years.

Their power on sequence is different from data sheet p88, and AVDD/DRVDD is last.

In this sequence, no POP heard.

The sequence is decided by customer themselves cut & try using actual board.

 

In case their co-operation company design this time, followed data sheet  and AVDD/DRVDD is 2nd and  DVDD is last.

In this sequence, POP heard.

Please refer  attached waveform.

 

 

Q1  We see power supply recommendation  in data sheet p88 , but what is the purpose ?

      Is sequence in data sheet for POP? or other reason? 

 

Q2  Do you think customer 's  sequence is wrong?

 

Best Regards

 

 

 

 

 

 

 

 

 

 

  • 0
    Mastermind 6205 points

     

    Dear Sirs,

     

    I can see that POP removed when AVDD/DRVDD comes last in TLV320AIC3101 EVM.( attached ppt),

    but this is different from power up recommendation on data sheet.

    Please allow me add one more question from customer.

     

    Q1  We see power supply recommendation  in data sheet p88 , but what is the purpose ?      

    Is sequence in data sheet for POP? or other reason?

     

    Q2  Do you think customer 's  sequence  ( DRVDD/AVDD  comes last ) is wrong?

     

    Q3   In additon to Q1 ,  What does following * mean?

    * Page 88 on d/s

    " The TLV320AIC3101 has been designed to be extremely tolerant of power supply sequencing.

    However, in some rare instances, unexpected conditions can be attributed to power supply sequencing."

     

    Q4  we  see you had add the power on sequence in the data sheet on 2010 Oct,

    but what is its background?

    https://e2e.ti.com/support/data_converters/audio_converters/f/64/t/70247   

     

    With my best regards

     

    TLV320AIC3101_POP_.pptx

     

     

  • 0 in reply to KANJI SHIBATANI
    TI__Mastermind 30220 points
    Shibatani-san

    I apologize for my delayed response. I have replied to your questions below, but i am awaiting on details regard your second question from the design team.

    q1: the power sequence was not written with pop in mind

    q2: As per the datasheet recommendations dvdd should always be less than or equal to AVDD. I will inquire with the design team regarding the rigidity of this recommendation

    q3: the power sequence is very flexible. I have been meaning to revise this power sequence to show the reset pin as well. The reset pin should be held low until all supplies are stable. We have seen rare instances where the device will be unresponsive if the reset pin is high and DVDD has not arrived at its proper value.

    q4: The power sequence was added because there is leakage current when t2 is longer than 5 ms.

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Mastermind 6205 points

    Dear Steve-san

    Thank you for your answer !

    I will wait your answer ( design-team answer ) about my question q2.

    In the Customer 's sequence , they set  /RESET pin low until all supply became stable.

    So, I think customer's sequence (AVDD/DRVDD comes last)  is no problem unless otherwise /RESET is High.

    Thank you for your support.

    Best Regrds

  • 0 in reply to KANJI SHIBATANI
    Mastermind 6205 points

    Dear Steve-san

    Dear Sirs,

     

    Would you please adivse about customer's power sequence **  is Okay or no ?

    My customer is waiting your answer, but they should release MCU software soon...

     

    ** customer's power sqquence **

     

    1  assert /RESET=L

    2 IOVDD goes high

    3 DVDD goes high

    4 AVDD/DRVDD goes high  ( AVDD/DRVDD comes last has No-POP )

    5 after all power rail became stable MCU assert  RESET = High

     

    Thank you for your support.

    Best Regards