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TLV320AIC3104: THD+N Issue with 48K sample rate

Wu JW
Intellectual 2935 points
Part Number: TLV320AIC3104

Hi, Team,

My customer test the THD+N ratio for the TLV320AIC3104 with different sample rate. They found the performance for THD+N with 48k sample rate have some issue, it is normal when the sample rate is 8K and 16K.

The detail info as in the attachment. It have the SCH and test result. Customer set the register with different sample rate as in our datasheet& application note said.

Could you give some suggestion for that? Thanks!THD.docx

  • 0
    TI__Mastermind 30030 points
    Wu,

    can you provide your register configuration for 48kHz?

    best regards,
    -Steve wilson
  • 0 in reply to Steve-Wilson
    Prodigy 50 points
    hi, Steve

    which register/registers configuration should I provide? or should I provide you all registers configutation?
  • 0 in reply to 玛格丽特的山茶花
    TI__Mastermind 30030 points
    hello,
    a full register dump would be preferable. Also, can you tell me if you are testing the performance on an EVM? or is this your own board?

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 50 points

    hi

    when sample rate is 8k, all registers config refer to 

    3104_register_config_for_8K.txt 
    dump all 3104 registers config as follows, when sample rate is 8K

register value frome 0x0  to 0xf : 0x0 0x0  0xaa 0x81 0x30 0x0  0x0  0xa  0x0 0x0  0x0 0x1  0x50 0x0  0x0  0x0
register value frome 0x10 to 0x1f: 0x0 0xff 0xff 0x4  0x78 0x78 0x7c 0x78 0x0 0xc6 0x0 0xfe 0x0  0x0  0xfe 0x0
register value frome 0x20 to 0x2f: 0x0 0x0  0x0  0x0  0xcc 0xc0 0x0  0x0  0x0 0x0  0x0 0x0  0x0  0x0  0x0  0x80
register value frome 0x30 to 0x3f: 0x0 0x0  0x80 0x2f 0x0  0x0  0x0  0x0  0x0 0x0  0x2 0x0  0x0  0x0  0x0  0x0
register value frome 0x40 to 0x4f: 0x0 0xf  0x0  0x0  0x0  0x0  0x0  0x0  0x2 0x0  0x0 0x0  0x0  0x0  0x0  0x0
register value frome 0x50 to 0x5f: 0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0 0x80 0x0 0x0  0x80 0x2b 0xce 0xc
register value frome 0x60 to 0x6f: 0x0 0x0  0x0  0x0  0x0  0x0  0x2  0x0  0x0 0x0  0x0 0x0  0x0  0x0  0x0  0x0
register value frome 0x70 to 0x7f: 0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0 0x0  0x0 0x0  0x0  0x0  0x0  0x0

    when sample rate is 48k, all registers config refer to 

    3104_register_config_for_48K.txt 
    dump all 3104 registers config as follows, when sample rate is 48K

register value frome 0x0  to 0xf : 0x0 0x0  0x0  0x10 0x4  0x0  0x0  0xa  0x0 0x0  0x0  0x1  0x50 0x0  0x0  0x0 
register value frome 0x10 to 0x1f: 0x0 0xff 0xff 0x4  0x78 0x78 0x7c 0x78 0x0 0xc6 0x0  0xfe 0x0  0x0  0xfe 0x0 
register value frome 0x20 to 0x2f: 0x0 0x0  0x0  0x0  0xcc 0xc0 0x0  0x0  0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x80 
register value frome 0x30 to 0x3f: 0x0 0x0  0x80 0x2f 0x0  0x0  0x0  0x0  0x0 0x0  0x2  0x0  0x0  0x0  0x0  0x0 
register value frome 0x40 to 0x4f: 0x0 0xf  0x0  0x0  0x0  0x0  0x0  0x0  0x2 0x0  0x0  0x0  0x0  0x0  0x0  0x0 
register value frome 0x50 to 0x5f: 0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0 0x80 0x0  0x0  0x80 0x2b 0xce 0xc 
register value frome 0x60 to 0x6f: 0x0 0x0  0x0  0x0  0x0  0x1  0x2  0x0  0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x0 
register value frome 0x70 to 0x7f: 0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x0

    and we are testing our own board, not an EVM board

  • 0 in reply to Steve-Wilson
    Prodigy 50 points

    hi,steve

    Is ther any progress about the issue? Hope to recieve your answer, thanks!

  • 0 in reply to 玛格丽特的山茶花
    TI__Intellectual 2935 points

    Hi, Steve,

    How about your suggestion? Thanks!

  • 0 in reply to Wu JW
    TI__Mastermind 30030 points
    Wu,

    Your setups are not similar. In the 8kHz register configuration you are using the PLL with a MCLK of roughly 8.192MHz. However in the 48khz register configuration you are using an MCLK of 12.288MHz. It seems strange that you would need to use different settings for these. For the 8k, and 16k, the PLL or CLKDIV setup should be exactly the same as the 48Khz, the only difference is the value of register 0x02

    Which MCLK frequency are you using? Is it possible that your MCLK= 8.192Mhz? and you just need to use the same PLL settings for the 48Khz register configuration?

    best regards,
    -Steve wilson
  • 0 in reply to Steve-Wilson
    Prodigy 50 points

    hi,steve

    sorry for delaying to reply you, as for we have a Chinese new year festival vacation!

    according to your advice, we set MCLK=8.192MHz when sample rate is 48k, and the issue still exits

    the registers configuration refer to

    3104_register_config_for_48K_new.txt 
    dump all 3104 registers config as follows, when sample rate is 48K

register value frome 0x0  to 0xf : 0x0  0x0  0x0  0x81 0x30 0x0  0x0  0xa  0x0 0x0  0x0 0x1  0x50 0x0 0x0  0x0 
register value frome 0x10 to 0x1f: 0x0  0xff 0xff 0x4  0x78 0x78 0x7c 0x78 0x0 0xc6 0x0 0xfe 0x0  0x0 0xfe 0x0 
register value frome 0x20 to 0x2f: 0x0  0x0  0x0  0x0  0xcc 0xc0 0x0  0x0  0x0 0x0  0x0 0x0  0x0  0x0 0x0  0x80 
register value frome 0x30 to 0x3f: 0x0  0x0  0x80 0x2f 0x0  0x0  0x0  0x0  0x0 0x0  0x2 0x0  0x0  0x0 0x0  0x0 
register value frome 0x40 to 0x4f: 0x0  0xf  0x0  0x0  0x0  0x0  0x0  0x0  0x2 0x0  0x0 0x0  0x0  0x0 0x0  0x0 
register value frome 0x50 to 0x5f: 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0 0x0  0x80 0x0 0x0  0x80 0x2b 0xce 0xc 
register value frome 0x60 to 0x6f: 0x0  0x0  0x0  0x0  0x0  0x0  0x2  0x0  0x0 0x0  0x0 0x0  0x0  0x0 0x0  0x0 
register value frome 0x70 to 0x7f: 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0 0x0  0x0 0x0  0x0  0x0 0x0  0x0
      when sample rate is 48k

    the registers configuration refer to

    5618.3104_register_config_for_8K.txt 
    dump all 3104 registers config as follows, when sample rate is 8K

register value frome 0x0  to 0xf : 0x0 0x0  0xaa 0x81 0x30 0x0  0x0  0xa  0x0 0x0  0x0 0x1  0x50 0x0  0x0  0x0
register value frome 0x10 to 0x1f: 0x0 0xff 0xff 0x4  0x78 0x78 0x7c 0x78 0x0 0xc6 0x0 0xfe 0x0  0x0  0xfe 0x0
register value frome 0x20 to 0x2f: 0x0 0x0  0x0  0x0  0xcc 0xc0 0x0  0x0  0x0 0x0  0x0 0x0  0x0  0x0  0x0  0x80
register value frome 0x30 to 0x3f: 0x0 0x0  0x80 0x2f 0x0  0x0  0x0  0x0  0x0 0x0  0x2 0x0  0x0  0x0  0x0  0x0
register value frome 0x40 to 0x4f: 0x0 0xf  0x0  0x0  0x0  0x0  0x0  0x0  0x2 0x0  0x0 0x0  0x0  0x0  0x0  0x0
register value frome 0x50 to 0x5f: 0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0 0x80 0x0 0x0  0x80 0x2b 0xce 0xc
register value frome 0x60 to 0x6f: 0x0 0x0  0x0  0x0  0x0  0x0  0x2  0x0  0x0 0x0  0x0 0x0  0x0  0x0  0x0  0x0
register value frome 0x70 to 0x7f: 0x0 0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0 0x0  0x0 0x0  0x0  0x0  0x0  0x0
     when sample rate is 8k

    acording to the datasheet, register 0x02 is meant for setting the divider, when configuting different sample rate, the register value is not same

    can we set aic3104 in this working mode: audio is be transferred to aic3104, and then 3104 outputs the collected audio data directly！If this is possible, which registers should I set?

  • 0 in reply to 玛格丽特的山茶花
    TI__Mastermind 30030 points
    hello,

    Your configurations are correct, can you provide scope captures of the I2S lines at 8khz?
    it may also be helpful if you provide your AP setup.

    regarding your last question, the AIC3104 does not have an internal path from the ADC to DAC. the DOUT pin can be shorted to the DIN pin if you are not using an external processor.

    best regards,
    -Steve wilson
  • 0 in reply to Steve-Wilson
    Prodigy 50 points

    hi, steve

    the following picture is our board sch. the soc works in I2S master mode, and aic3104 works in I2S slave mode.

    the mclk is generated by the SoC, and when sample rate is 48k, the mclk must be 12.288MHz. So we can not set 3104 in 8.192MHz, when 48k

    and the I2S signial refer to the attachmentline_out.rar

  • 0 in reply to 玛格丽特的山茶花
    TI__Mastermind 30030 points
    hello,

    The schematic did not come through, can you try posting again?

    regarding your I2S signal, would you mind taking a pic that shows the Data, WCLK, and BCLK all on the same screen? please trigger to WCLK.

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    TI__Mastermind 30030 points
    Wu,
    I did not hear back from you. were you able to resolve this issue?

    best regards,
    -Steve Wilson