TLV320AIC3268: Problems with mixing two I2S signals

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Anthony Yoo68

Replies: 4

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Part Number: TLV320AIC3268

Hi!

My customer is developing a concept that mixes two I2S signals and outputs them as one I2S.

It is being tested using Purepath GDE and Purepath concole2.

Below is a block I made using GDE for testing.

However, I2S audio source mixed with ASI3 is not output (bit clock, word clock, D out)To do this, I used Purepath concole2 to change the ASI3 setting in Register Page4,

But I still have not found the properly solution.

For reference, change the block as shown below to change the I2S output to ASI1, and check that the digital out data is normally output.

But this is not what customers want.

The customer wants to change the mixed data to the required sampling frequency and output the I2S to ASI3.

Is there a solution that can solve this problem by changing other sets or modifying GDE blocks?

Thank you.

Best regards

From Anthony

• TLV320AIC3268

Expert 1320 points

Anthony Yoo68

• Feb 10, 2019 3:26 AM
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4 Replies

• Guru 57780 points

  

  Diego Melendez

  

  • Feb 11, 2019 10:47 PM

  Hi, Anthony,

  Can you please provide more details about the required sampling rate and audio serial interface specs for customer?. Please keep in mind that the codec can run in a single sampling rate only, and cannot interface between different interfaces if the sampling rate is not the same.

  Best Regards,

    -Diego Meléndez López
     Audio Applications Engineer

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• Expert 1320 points

  

  Anthony Yoo68

  

  • Feb 12, 2019 4:16 PM

  In reply to Diego Melendez:

  Hi!

  Thank you for your resply.

  As you said, I have unified the sampling frequency of the I2S source and confirmed that the mixing works well.

  have confirmed that the two I2S sources input as ASI1 and ASI2 are mixed and output to ASI2 (Dout).(I tested it by synchronizing the bit clock and word clock input to ASI2 to the ASI3 output port (GPIO1, GPIO2)

  using the purepath consol2 register setting and connecting the output(ASI3 bit clock(GPIO1), word clock(GPIO2)) to the amp with ASI2 Dout.

  However, mixing I2S sources from ASI1 and ASI2 and exporting them to ASI3 is not implemented yet.

  I want the following concept. ASI1 (I2S input source from CPU) + ASI2 (I2S input source from BT module) ==> ASI3 (I2S Out source to AMP)

  

  Is it impossible to actually implement the above concept?If possible, can I show me an example (GDE block or source code or another tip)?Please help me.

  If you have any more details, please let me know.

  Please help me.

  Thank you

  Best regards

  From anthony

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• Expert 1320 points

  

  Anthony Yoo68

  

  • Feb 17, 2019 11:51 PM

  In reply to Anthony Yoo68:

  Hi Diego

  Could you check the above questions?

  Attach my customer's schematic to my question to make it easier for you to understand.

  Please check it.

  Thank you.

  Best regards

  From Anthony.

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• Expert 1320 points

  

  Anthony Yoo68

  

  • Mar 5, 2019 2:40 PM

  In reply to Anthony Yoo68:

  Hello~
  Gentle Reminder
  Please help me!!
  
  Thank you
  Best Regards

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