[FAQ] TLV320AIC3120: Change sampling frequency dynamically on the TLV320AIC3120

When changing clock settings, assuming AIC3120.

1) Keep MCLK running for current sample rate.

2) Power Down ADC and DACs.

3) Wait for ADC and DAC powerup flags to clear (time may vary upon soft-stepping setting). This is on page 0, registers 36 and 37.

4) Shut down PLL

5) External MCLK signal can now be changed, if necessary.

6) If codec is I2S master, set BCLK divider properly.

7) Change PLL settings and powerup PLL.

8) Wait 10ms for PLL to lock.

9) Set clock divider values (e.g. DOSR, MDAC, NDAC, AOSR, MADC, NADC) as well as miniDSP settings (i.e. interpolation/decimation factors).

10) Power-up ADC and DACs when desired.