This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPA3221: THD+N in PBTL AD Modulation

Part Number: TPA3221

Hi,

A customer is going to use TPA3221 by PBTL AD Modulation.
He says that his measurement data of TPA3221EVM THD+N is not less than 0.05 percent.
And it is worse than Typical Characteristics of the datasheet.

Q: Did the figures in 7.9 Typical Characteristics measure TPA3221EVM?

Please teach us, if you know how to get good THD+N data, except for measurement conditions described in datasheet.

Best regards,

Akio Ito

  • Hello,
    does customer select inductor as what EVM referenced? normally THD imapct by inductor selection.

    Regards
    Linda
  • Hello, Linda-san,

    Thank you for your answer. But I do not agree with you.
    Because the board which our customer measured was a TPA3221EVM.

    Best regards,
    Akio Ito
  • Hi Akio,

    Can you show us the THD+N that you are seeing, preferably a frequency or output power sweep? Also please share more about your setup configuration such as the gain, PVDD level, load, etc.

    Thank you,
    Robert Clifton
  • Hello, Robert-san,

    Thank you for your reply. Now I am requesting the THD+N measurement data to our customer.
    Please wait for a few days.

    Best regards,
    Akio Ito
  • Hi Akio-san,

    Thank you for letting me know.

    Best Regards,
    Robert Clifton
  • Hello, Robert-san,

    I got the TPA3221EVM THD+N measurement data from our customer. The measurement data is shown below.

    <Measurement condition>
    Load: 2Ω
    Signal: f=1kHz
    PVDD: 30V
    VDD: On board(TPA3221EVM)

    <Measuring instrument>
    APX-585 I/O: analog balanced, filters: AES17(20kHz)
    AUX0025

    <TPA3221EVM Configuration>
    INPUT 1: DIFF IN1(J14)
    Gain/SLV Select(J23): MSTR-18dB
    HEAD(J6): AD
    FREQUENCY ADJUST(J16): MASTER MODE(600 kHz)
    IN2P(J7)/IN2M(J8): PBTL

    The comments from our customer is below.

    The maximum output power meets the specification, but THD + N does not reach the expected value.
    Can you give me advice if there is anything to be careful about measurement?

    Best regards,

    Akio Ito

  • Hello Akio-san,

    So the expected value that the customer was trying to reach was based in the datasheet I presume?

    If this is the case there was a few differences between the datasheet and the EVM in terms of setup.  The datasheet is showing pre-filter PBTL rather than post-filter PBTL mode. The difference between these modes is where you tie the outputs of the amplifier together and how many inductors you needs.  I'm assuming that the customer is using Post filter PBTL mode (using 4 inductors). That might raise the THD+N to what they are seeing.  

    There might be a difference in which inductors were used on the EVM from what data was used in the datasheet which as Linda mentioned could create a difference in the THD levels.

    I'll double check to see if I get a similar THD+N vs Power curve as the customer to verify that nothing is wrong in the setup.

    Best Regards,

    Robert Clifton

  • Hello, Robert-san,

    Thank you for your reply. After you done the THD+N double check, please let us know its result.

    Best regards,

    Akio Ito
  • Hello Akio-san,

    I ran the THD+N vs Power test to see if I was getting similar results. For the most part I was able to recreate a very similar THD+N vs Power curve. However the results you showed me had a slightly higher THD+N at 10mW, which suggest the noise floor is higher in the customer's system.

    I'd recommend trying pre-filter PBTL mode if they want to lower the THD+N further.

    Best Regards,
    Robert Clifton
  • Hello, Robert-san,

    Thank you for checking the THD+N versus Power of TPA3221EVM.
    Our customer replied that he found his measurement method was correct, as you were able to recreate a very similar THD+N vs Power curve.

    He made a pre-filter PBTL mode prototype board and measured its THD+N vs Power as shown below.

    <Measurement condition>
    Load: 2Ω
    Signal: f=1kHz
    PVDD: 30V
    VDD: On board (the prototype board)

    <Measuring instrument>
    APX-585 I/O: analog balanced, filters: AES17(20kHz)
    AUX0025

    <TPA3221EVM Configuration>
    Gain/SLV: -18dB/Slave
    HEAD: AD mode
    OSCM/OSCP: External 3MHz clock (PWM: 500kHz)
    Input signal: Differential IN1_P,IN1_N
    Output configuration: PBTL (IN2_P and IN2_M tied to GND)
    LC filter: the values are same as Figure 51 of TPA3221 datasheet

    His comments with measurement data is below.

    The maximum output power meets the specification, but THD+N does not reach the expected value.
    Does external clock in slave mode degrade THD+N?

    And he said he will try pre-filter PBTL mode on TPA3221EVM.


    Best regards,

    Akio Ito

  • Hi Akio-san,

    When you say he made a proto-type board, are you saying he modified the TPA3221EVM to use Pre-filter PBTL mode?

    I'm very surprised with the THD+N curve he is showing. I'd first check to see if the results look like this if he sets the device's switching frequency to one of the Master modes first, to ensure that it's not the external oscillator that is causing issues. Let me know if that improves the results!

    Best Regards,
    Robert Clifton
  • Hello, Robert-san,

    I did not know he had been making a proto-type board for their product until he sent to us its THD+N vs Power data.

    Their product use multiple D-AMPs, and they are afraid of beats of switching power supplies and D-AMP clocks.
    So, they will drive multiple TPA3221 in slave mode by external oscillator.
    A few months ago, I have suggested to him using a D-flipflop clock divider to keep 50 percent duty cycle for TPA32xx slave mode external clock.
    I also think he should first compare THD + N in master mode and slave mode on his proto-type board. I will ask him for that.

    Best regards,

    Akio Ito

  • Hi Akio-san,

    Depending on how many TPA3221 devices are on the board, I'd recommend having the devices out of phase by 120 degrees.

    This will allow the power supply to not be as strained when the FETs are switching since each IC will be switching at different times.

    Best Regards,
    Robert Clifton