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TLV320AIC3104: MIC adc channel shutdown problem

cetinbattal
Prodigy 90 points
Part Number: TLV320AIC3104

Hi,

I have  a problem about mic channel,

I want to activate only one mic channel for example MIC1LP/MIC1LM, I set  register 19(MIC1LP) to 0x04 , register 22(MIC1RP)  setted to 0x00, but Two channels(MIC1LP - MIC1RP) continue to transmit sound.

Other case, if i activate two channel (register 19 & register 22  -->0x04) and  shutdown only register 22 -->0x00, it  continue to transmit sound. i set register 19 to 0x00 ,all mic channel(MIC1LP - MIC1RP) is muted. Register 16 is about MIC1LP but it affect all channel.

Do you have any suggesitons about only one channel shutdown or activation?

  • 0
    TI__Mastermind 30030 points
    User,

    Can you read registers 0x0f -0x25 and send them to me?

    Note that MIC1LP is controlled by register 19 AND 24 (left and Right ADC respectively)
    and MIC1RP is controlled by Registers 21 AND 22 (Left and right ADC respectively)

    Note also that register 19 bits D3-D7 refer to MicL1 however bits D0-D2 refer to the LEFT ADC and LEFT PGA. The left ADC and PGA can be fed by many inputs. This is also true of register 22. Bits D0-D2 control the RIGHT ADC and Right PGA.

    Please refer to the functional block diagram in the data sheet for clarity.

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 90 points
    Hi Steve,

    my start-up registers:

    0x0F --> 0x00
    0x10 --> 0x00
    0x11 --> 0xFF
    0x12 --> 0xFF
    0x13 --> 0x00
    0x14 --> 0x78
    0x15 --> 0x78
    0x16 --> 0x00
    0x17 --> 0x78
    0x18 --> 0x78
    0x19 --> 0xC0
    0x1A --> 0x00
    0x1B --> 0xFE
    0x1C --> 0x00
    0x1D --> 0x00
    0x1E --> 0xFE
    0x1F --> 0x00
    0x20 --> 0x00
    0x21 --> 0x00
    0x22 --> 0x00
    0x23 --> 0x00
    0x24 --> 0x00
    0x25 --> 0xC0


    if i want to activate only MIC1RP channel and register 22 set to 0x04, but MIC1RP channel didnt activate.

    İf i change register 19 to 0x04 all channel(MIC1RP & MIC1LP) activates, İ want to activate onyly one channel(MIC1RP or MIC1LP).
  • 0 in reply to cetinbattal
    TI__Mastermind 30030 points
    User,

    Your configuration looks good to me. I can test this on an EVM and It works as it is supposed to.

    1. are you certain that you are getting both Mic1RP and Mic1LP? is it possible that mic1LP is being repeated?
    2. is your WCLK a square wave with frequency fs? or is it possible that it is a short pulse?

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 90 points
    1. are you certain that you are getting both Mic1RP and Mic1LP? is it possible that mic1LP is being repeated?
    one mic connects MIC1LP- MIC1LM, other mic connects MIC1RP-MIC1RM port,
    2. is your WCLK a square wave with frequency fs? or is it possible that it is a short pulse?
    i measured clock signal pins , mclk 12Mhz, bclk 512khz, wclk 16khz ,All signal forms are good.My audio codec is master. Register 2 setted to 0x44
  • 0 in reply to cetinbattal
    TI__Mastermind 30030 points
    cetinbattal,

    1. I can see that the mics are connected to different ports. My Question refers to the data output. Is it possible that the data in the right data slot is actually repeated left data?

    2. This looks good. I ask because the I2S setting does not like abnormal wCLKs and Ive seen strange things happen where the left data gets repeated on the right slot.

    Can you send me your registers 2-9?

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 90 points

    1. I can see that the mics are connected to different ports. My Question refers to the data output. Is it possible that the data in the right data slot is actually repeated left data? 

    Sorry i dont understand, What Does data output mean HPLout, LOP_M or DAC status ?

    2. This looks good. I ask because the I2S setting does not like abnormal wCLKs and Ive seen strange things happen where the left data gets repeated on the right slot. 

    Can you send me your registers 2-9?

    0x02 --> 0x44

    0x03 --> 0x91

    0x04 --> 0x20

    0x05 --> 0x1E

    0x06 --> 0x00

    0x07 --> 0x0A

    0x08 --> 0xC0

    0x09 --> 0x00

  • 0 in reply to cetinbattal
    TI__Mastermind 30030 points
    cetinbattal,

    1. data output = DOUT. for I2S, there are two Data slots, what I'm asking is... Are you 100% positive that the data on the "right" slot is coming from the RIGHT ADC. is it possible that the LEFT ADC data is getting repeated on the right Data output?
    This would be pretty easy to test.

    2. so your MCLK is 12Mhz, and you are running the CODEC as the I2S Master. correct? you are running the Codec with an FS of 16khz. a word length/bit depth of 16bits, and the data format is I2S.

    Does this all match up with your processor? are you getting any overflow/underflow flags on the processor end?

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    TI__Mastermind 30030 points
    Cetinbattal,

    Were you able to resolve your issue? I am happy to continue troubleshooting this with you. Please let me know if you need more assistance.

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 90 points

    Hi Steve,

    Sorry for late answer, I was interested in another problem,

    1. data output = DOUT. for I2S, there are two Data slots, what I'm asking is... Are you 100% positive that the data on the "right" slot is coming from the RIGHT ADC. is it possible that the LEFT ADC data is getting repeated on the right Data output? 
    This would be pretty easy to test. 

    i am sure but i can try it, please tell stages

    2. so your MCLK is 12Mhz, and you are running the CODEC as the I2S Master. correct? you are running the Codec with an FS of 16khz. a word length/bit depth of 16bits, and the data format is I2S. 

    Yes to all. Register 9 is 0x00(for 16 bit).

    Does this all match up with your processor? are you getting any overflow/underflow flags on the processor end?

    Yes i have overflow flag, register 11 is 0xC1

  • 0 in reply to cetinbattal
    TI__Mastermind 30030 points
    cetinbattal,

    I will use your register configuration and set this up on my EVM, and see what we get.

    -Steve
  • 0 in reply to Steve-Wilson
    Prodigy 90 points

    Thank you Steve, I am waiting your test..

  • 0 in reply to Steve-Wilson
    Prodigy 90 points

    Hi Steve,

    Did you find something?

    Thanks,

  • 0 in reply to cetinbattal
    TI__Mastermind 30030 points
    Cetinbattal,

    No. When I run your configuration, I get expected behavior. If I set register 0x13 to 84, and register 16 to 0x84, and I then set register 0x13 to 00, I only get signal on the right channel. When I do the opposite, and I set register 0x16 to 0x00, then I get the left channel only.

    I suspect your processor is incorrectly interpreting the data, or there is a command error of some kind.

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 90 points
    Hi Steve,
    MCLK=2Mhz BCLK=512 KHz and WCLK=16KHz,
    And my codec is Master,
    And my PLL register,

    0x02 -> 0x44
    0x03 -> 0x91
    0x04 -> 0x20
    0x05 -> 0x1E
    0x06 -> 0x00
    0x07 -> 0x0A
    0x08 -> 0xC0
    0x09 -> 0X00
    0x0A -> 0x00
    0x0B -> 0x01

    0x66 -> 0x02

    Do you think there is an error?
  • 0 in reply to cetinbattal
    TI__Mastermind 30030 points
    Cetinbattal,

    Yes. There is an issue. You said the MCLK was 12Mhz. now you are saying it is 2Mhz.

    With 12Mhz the PLL configuration will work beautifully with 2Mhz, it is all wrong.

    What is the MCLK frequency?

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Prodigy 90 points

    Hi Steve,

    Sorry for this, my keyboard fault,

    MCLK is 12MHz.

  • 0 in reply to cetinbattal
    TI__Mastermind 30030 points
    Cetinbattal,

    I tested this in master mode, with the settings you provided, with DOUT shorted to DIN. I don't experience any issue. I believe this is an issue on the processor end.

    best regards,
    -Steve Wilson