TLV320DAC3120: Noisy output

Hi, Radomir,

Welcome to E2E and thank your for your interest in our products!

I have few observations regarding your registers settings.

Just to confirm, do you have BCLK = 2.304MHz and WCLK = 36KHz?

If so, it seems that your PLL settings are incorrect, please verify my calculations below and let me know if I made a mistake:

The PLL settings seem to be configured as J = 8, P = 1, R =1, D = 0. If BCLK is selected as PLL_input_clock, this will result in a PLL clock = 18.432 MHz. Based on the PLL section of the datasheet ( http://www.ti.com/lit/ds/symlink/tlv320dac3120.pdf#page=46 ), the PLL clock must be in a range of 80MHZ to 110MHz. So, you would need to increase the PLL clock frequency to achieve this range.

Then, the configured sampling rate seems to be too low. The fs = PLL_CLK / (MDAC x NDAC x DOSR) = 18.432MHz / (8 x 2 x 128) = 9 KHz. This value should be equal than the WCLK frequency (32KHz).

Finally, it seems that you have configured a BCLK offset in the I2S protocol with the page 0 / register 28. Did you consider your I2S communication lines to send the data after the first 2 BCLK pulses of each channel (after the falling or rising edge of the WCLK)?

Another recommendation is to add a low pass filter at the TLV320DAC3120 headphone output  (in case you are getting the noise at this output). The DAC devices have a delta-sigma converter that generates a lot of high-frequency noise. When the output is connected to an amplifier, this noise can be increased. Please take a look at the following document for details:

http://www.ti.com/lit/an/slaa313/slaa313.pdf

Also, I attached my registers settings analysis. It is in format w 30 xx yy (w: write command, 30: i2c address, xx = register address, yy = register data).

w 30 00 00 # Page 0
w 30 01 01 # Reset
w 30 04 07 # BCLK = 2.304MHz as PLL_INPUT; PLL_CLK selected
w 30 05 91 # PLL on; P = 1; R = 1
w 30 06 08 # J = 8
w 30 07 00 # D = 0
w 30 08 00
w 30 1b 00 # 16-bits; I2S; BCLK/WCLK as inputs
w 30 1c 02 # Data offset 2 BCLKs
w 30 0b 82 # N = 2
w 30 0c 88 # M = 8
w 30 0d 00 # DOSR = 128
w 30 0e 80
w 30 3c 19 # PRB_P25
w 30 3d 05 # Reserved
w 30 25 90 # Read only register
w 30 00 08 # Page 8
w 30 01 04 # Adaptive filtering
w 30 00 01 # Page 1
w 30 1f 1c # CMV = 1.8V
w 30 2a 04 # Class-D amp not muted, 6dB gain
w 30 20 86 # Class-D amp on
w 30 21 4e # Pop removal settings
w 30 23 40 # DAC routed to the mixer amp
w 30 24 80 # Analog volume routed to HPOUT
w 30 1f 84 # HPOUT on; CMV = 1.35V
w 30 28 06 # HPOUT not muted; 0dB gain
w 30 26 00 # Analog volume routed to Class-D driver
w 30 2e 0b # MICBIAS = AVDD; MICBIAS powered up
w 30 00 00 # Page 0
w 30 3f 96 # DAC on; DAC to left data; Soft-stepping disabled
w 30 40 04 # DAC not muted
w 30 41 00 # DAC gain = 0dB

Please let me know if you have additional questions or comments on this.

Best regards,
Luis Fernando Rodríguez S.

Hi, Radomir,

Excuse me, do you have a feedback on this?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Hi, Radomir,

I will close this E2E thread for now. But feel free to provide your feedback or your comments on this in case you have additional observations. We will be glad to help you.

Best regards,
Luis Fernando Rodríguez S.

Hi

Sorry I didn't answer it was just a busy two days.

We have made the changes with your init file but it still does not work. We have checked the I2S again, but it looks good. Are there other settings outside of the PLL that can be adjusted or make it not work?

Best regards,

Radomir Pans 

Hi, Radomir,

Could you provide your updated registers settings, please? This will help us to have a better approach to the issue.

Best regards,
Luis Fernando Rodríguez S.

Hi, Radomir,

Do you have any feedback on this? Is it possible to provide your updated registers settings for further support? Any other observation or change these days?

Thank you.

Best regards,
Luis Fernando Rodríguez S.